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參數(shù)資料
| 型號(hào)： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁(yè)數(shù)： | 72/74頁(yè) |
| 文件大?。?/td> | 1061K |
| 代理商： | LXT970A |
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LXT970A
—
Dual-Speed Fast Ethernet Transceiver
72
Datasheet
19.2
100BASE-FX
1 = Enable 100BASE fiber interface.
0 = Enable 100BASE twisted-pair interface.
R/W
Note 6
19.1
Reserved
Write as 0; Ignore on read.
R/W
0
19.0
Transmit
Disconnect
1 = Disconnect TP transmitter from line.
0 = Normal operation.
R/W
0
Table 56. Chip Status Register (Address 20, Hex 14)
Bit
Name
Description
Type
1
Default
20.15:1
4
Reserved
Ignore on read.
RO
N/A
20.13
Link
1 = Link is up.
0 = Link is down.
Link bit 20.13 is a duplicate of bit 1.2, except that it is a dynamic
indication, whereas bit 1.2 latches Low.
RO
0
20.12
Duplex Mode
1 = Full-duplex.
0 = Half-duplex.
RO
Note 2
20.11
Speed
1 = 100 Mbps operation.
0 = 10 Mbps operation.
RO
Note 2
20.10
Reserved
Ignore on read.
RO
N/A
20.9
Auto-Negotiation
Complete
1 = Auto-negotiation process complete.
0 = Auto-negotiation process not complete.
Auto-Negotiation Complete bit 20.9 is a duplicate of bit 1.5.
RO/LH
0
20.8
Page Received
1 = Three identical and consecutive link code words have been
received.
0 = Three identical and consecutive link code words have not been
received.
Page Received bit 20.8 is a duplicate of bit 6.1
RO/LH
0
20:7
Reserved
Ignore on read.
RO
0
20.6
Reserved
Ignore on read.
RO
0
20.5
Reserved
Ignore on read.
RO
N/A
20.4
Reserved
Ignore on read.
RO
N/A
20.3
Reserved
Ignore on read.
RO
N/A
20.2
Low-Voltage
1 = Low-voltage fault on VCC has occurred.
0 = No fault.
RO
N/A
20.1
Reserved
Ignore on read.
RO
N/A
20.0
Reserved
Ignore on read.
RO
N/A
1. RO = Read Only
LH = Latching High (This bit remains High until read, and then returns Low).
2. Bits 20.12 and 20.11 reflect the current operating mode of the LXT970A.
Table 55. Configuration Register (Address 19, Hex 13) (Continued)
Bit
Name
Description
Type
1
Default
1. R/W = Read/Write
2. The default value of bit 19.13 is determined by pin MF1.
3. If auto-negotiation is disabled, the default value of bit 19.8 is determined by pin CFG1. If auto-neg is enabled, the default
value of bit 19.8 = 0.
4. The default value of bit 19.4 is determined by pin MF2 Operation.
5. The default value of bit 19.3 is determined by pin MF3 Operation.
6. If auto-negotiation is disabled, default value of bit 19.2 is determined by pin MF4. If auto-negotiation is enabled, default value
of bit 19.2 = 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT970 | Fast Ethernet Transceiver |
| LXT970QC | Fast Ethernet Transceiver |
| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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