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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網收發(fā)器 |
| 文件頁數(shù)： | 27/74頁 |
| 文件大小： | 1061K |
| 代理商： | LXT970A |
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Dual-Speed Fast Ethernet Transceiver
—
LXT970A
Datasheet
27
2.3
Operating Requirements
2.3.1
Power Supply Requirements
The LXT970A requires a 5V power supply. Power should be supplied from a single source to the
VCC, VCCA, VCCT, and VCCR power pins. A ground return path must be provided to the GND,
GNDA, GNDT, and GNDR pins. As a matter of practice, the power supply should be as clean as
possible. Filtering is recommended for the analog power pins (VCCA, VCCT, VCCR) at least in
the initial design. Consult the Design Recommendations section on
page 42
for details. A
decoupling capacitor is recommended between each VCC pin and its respective GND, placed as
close to the device as possible.
2.3.1.1
Optional MII Power Supply
The MII may be powered by either a 3.3V or 5V source via the VCCIO pin. To avoid power
sequencing issues, the VCCIO pin should be supplied from the same source used to power the
other side of the MII interface. When VCCIO is supplied with 3.3V, the MII inputs are not tolerant
of 5V signal levels. The MDIO and MDC pins must be operated at the same voltage as the rest of
the MII interface.
2.3.2
Reference Clock Requirements
The LXT970A requires a continuous, stable reference clock. There are two clock modes, Master
Clock Mode and Slave Clock Mode. Depending on the mode of operation, the clock may be
supplied at the crystal oscillator pins (XI, XO), or at the Transmit Clock pin (TX_CLK). See
Table
25 on page 48
for input clock requirements.
Table 14. LXT970A Operating Configurations / Auto-Negotiation Disabled
Desired Configuration
1,2
Pin Name
Input Value
MDIO Registers
Force 100FX Operation
MF4
V
MF
2, V
MF
3
19.2 = 1
CFG0
High
0.13 = 1
MF3
V
MF
1, V
MF
4
19.3 = 0
Force 100TX Operation
MF4
V
MF
1, V
MF
4
19.2 = 0
CFG0
High
0.13 = 1
Force 10T Operation
MF4
V
MF
1, V
MF
4
19.2 = 0
CFG0
Low
0.13 = 0
Force Full-Duplex Operation
FDE
High
0.8 = 1
Disable 10T Link Test
CFG1
High
19.8 = 1
Enable 10T Link Test
CFG1
Low
19.8 = 0
1. Refer to
Table 12
for basic configurations.
2. Refer to
Table 13
for Hardware Control Interface functions available when auto-negotiation is enabled.
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