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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 13/74頁 |
| 文件大?。?/td> | 1061K |
| 代理商： | LXT970A |
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Dual-Speed Fast Ethernet Transceiver
—
LXT970A
Datasheet
13
Table 4. LXT970A Twisted-Pair Interface Signal Descriptions
Pin#
1
Pin Name
I/O
2
Signal Description
21
23
TPOP
TPON
AO
Twisted-Pair Output, Positive and Negative
. Differential driver pair produces 802.3-
compliant pulses for either 100BASE-TX or 10BASE-T transmission.
20
TREF
AO
Transmit Reference
. Tie to center tap of output transformer.
29
30
TPIP
TPIN
AI
Twisted-Pair Input, Positive and Negative
. Differential input pair for either 100BASE-TX
or 10BASE-T reception.
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog
Table 5. LXT970A LED Indicator Signal Descriptions
Pin#
1
Pin Name
I/O
2
Signal Description
3
38
LEDS
O
Speed LED
. Active Low output indicates 100 Mbps operation is selected.
42
LEDR
O
Receive LED
. Active Low output indicates that receiver is active.
41
LEDT
O
Transmit LED
. Active Low output indicates transmitter is active.
40
LEDL
O
Link LED
. Active Low output;
During 100 Mbps operation, indicates scrambler lock and receipt of valid Idle codes.
During 10 Mbps operation, indicates Link Valid status.
39
LEDC
O
Collision LED
. In default mode, active Low output indicates collision. However, LEDC is
programmable and may be set for other indications. For programming options, see
Configuration Register 19 in
Table 55,
“
Configuration Register (Address 19, Hex 13)
”
on
page 71
.
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
3. LEDs are read at power-up to determine scrambler seed values.
Table 6. LXT970A Miscellaneous Signal Descriptions
Pin#
1
Pin Name
I/O
2
Signal Description
10
TEST
I
Test
. Must be tied Low.
12
11
XI
XO
I
O
Crystal Input and Output
. Use a clock at XI or connect a 25 MHz crystal oscillator across
XI and XO. Refer to the Functional Description section for detailed clock requirements on
page 18
.
25
RBIAS
AI
Bias Control
. Controls operating circuit bias via an external 22.1 k
,
1% resistor to
ground.
16
RESET
I
Reset
. This active Low input is OR
’
ed with the control register Reset bit (0.15). The
LXT970A reset cycle is extended 300
μ
s (nominal) after Reset is de-asserted.
34
PWRDWN
I
Power Down
. When High, forces LXT970A into power down mode. This pin is OR
’
ed with
the Power Down bit (0.11). Refer to
Table 45
for more information.
32, 35,
36
N/C
-
No Connection
. Leave open.
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
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| LXT970 | Fast Ethernet Transceiver |
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相關(guān)代理商/技術(shù)參數(shù) |
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| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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