
LXT970A —
Dual-Speed Fast Ethernet Transceiver
4
Datasheet
2.8.2.3 Carrier Sense (CRS).................................................................38
Twisted-Pair PMD Layer ........................................................................39
2.8.3.1 Scrambler/Descrambler (100TX Only)......................................39
2.8.3.2 Baseline Wander Correction
(100TX Only)39
2.8.3.3 Polarity Correction.....................................................................39
Fiber PMD Layer....................................................................................39
Additional Operating Features ...............................................................40
Low-Voltage-Fault Detect.......................................................................40
Power Down Mode.................................................................................40
Software Reset.......................................................................................40
Hardware Reset .....................................................................................40
Application Information
.........................................................................................41
3.1
Magnetics Information.........................................................................................41
3.2
Crystal Information..............................................................................................41
3.3
Design Recommendations..................................................................................42
3.3.1
General Design Guidelines ....................................................................42
3.3.2
Power Supply Filtering ...........................................................................42
3.3.3
Ground Noise.........................................................................................43
3.3.4
Power and Ground Plane Layout Considerations..................................43
3.3.5
Interfaces for Twisted-Pair /Fiber...........................................................43
3.3.5.1 Twisted-Pair ..............................................................................43
3.3.5.2 Fiber..........................................................................................44
3.3.6
Interface for the MII................................................................................44
3.3.6.1 Transmit Hold Time Adjustment................................................44
3.3.6.2 MII Terminations........................................................................44
3.3.7
Typical Application .................................................................................45
3.3.7.1 Voltage Divider For MF Inputs...................................................45
Test Specifications
..................................................................................................47
Register Definitions
................................................................................................63
Mechanical Specifications
...................................................................................73
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.8.9
3.0
4.0
5.0
6.0