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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 40/74頁 |
| 文件大小： | 1061K |
| 代理商： | LXT970A |
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LXT970A
—
Dual-Speed Fast Ethernet Transceiver
40
Datasheet
2.8.5
Additional Operating Features
2.8.6
Low-Voltage-Fault Detect
The LXT970A low-voltage fault detection function prevents transmission of invalid symbols when
VCC goes below normal operating levels. If this condition occurs, the LXT970A disables the
transmit outputs and sets 20.2 = 1. Operation is automatically restored when V
CC
returns to
normal.
Table 26 on page 49
indicates voltage levels that detect and clear the low-voltage fault
condition.
2.8.7
Power Down Mode
The LXT970A goes into power down mode when PWRDWN is asserted. In this mode, all
functions are disabled except the MDIO. The power supply current is significantly reduced. This
mode can be used for energy-efficient applications or for redundant applications where there are
two devices and one is left as a stand-by. When the LXT970A is returned to normal operation,
configuration settings of the MDIO registers are maintained. Refer to
Table 22 on page 47
for
power down specifications.
2.8.8
Software Reset
Software reset causes all state machines to be reset and the LXT970A to re-configure itself to the
settings of the hardware configuration pins (MF<4:0>, FDE, CFG0, CFG1).
The LXT970A is reset via software(0.15 = 1). This bit setting is maintained while the reset
operation is running. When the reset operation is complete, the LXT70 resets bit 0.15 = 0.
2.8.9
Hardware Reset
Hardware reset causes the LXT970A to reset all of its functions and re-configure itself based on the
hardware configuration pin settings.
The LXT970A performs a hardware reset when a Low signal is detected at the RESET pin. All
operational conditions must be met for this function to operate. V
CC
must be above 4.75V and
stable, and the RESET signal must be asserted for two cycles of the master input clock. The
LXT970A continues to drive an internal reset for a period of 300
μ
s after the RESET signal is de-
asserted to ensure that all functions start up smoothly. MII registers are not available and the MDIO
output is tri-stated during the internal reset period. Refer to
Table 43 on page 62
for hardware reset
specifications.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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