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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 35/74頁 |
| 文件大?。?/td> | 1061K |
| 代理商： | LXT970A |
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Dual-Speed Fast Ethernet Transceiver
—
LXT970A
Datasheet
35
2.7
10BASE-T Operation
2.7.1
10BASE-T MII Operations
The MAC transmits data to the LXT970A over the MII interface. The LXT970A converts the
digital data from the MAC into an analog waveform that is transmitted to the network via the
copper interface. The LXT970A converts analog signals received from the network into a digital
format suitable for the MAC. The LXT970A sends the received data to the MAC via the MII. The
5-bit symbol code is not used for 10BASE-T operation. The MII operates only as a 4-bit interface
and the RXD4 & TXD4 lines are not used.
2.7.2
10BASE-T Network Operations
During 10BASE-T operation, the LXT970A transmits and receives Manchester-encoded data
across the network link. When the MAC is not actively transmitting data, the LXT970A sends out
link pulses on the line.
In 10BASE-T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded
signals received from the network are decoded by the LXT970A and sent across the MII to the
MAC.
The LXT970A does not support fiber connections at 10 Mbps.
2.8
Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT970A is a Physical Layer 1 (PHY)
device. The LXT970A implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u specification. The following paragraphs discuss LXT970A operation
from the reference model point of view.
2.8.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function when the MII is operating as a 4B interface.
For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line
driver as long as TX_EN is de-asserted.
When the MII is operating in 5B mode, the encoder/decoder function is disabled, and symbol data
presented at the MII is transparently passed downstream, and vice versa.
For 10T operation, the PCS layer merely provides a bus interface and serialization/de-serialization
function. 10T operation does not use the 4B/5B encoder, and is not supported when the MII is in
5B mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT970 | Fast Ethernet Transceiver |
| LXT970QC | Fast Ethernet Transceiver |
| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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