- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377799 > LXT970A (Intel Corp.) Dual-Speed Fast Ethernet Transceiver PDF資料下載
參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 5/74頁 |
| 文件大?。?/td> | 1061K |
| 代理商： | LXT970A |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
Datasheet
5
Dual-Speed Fast Ethernet Transceiver
—
LXT970A
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
LXT970A Block Diagram.......................................................................................9
LXT970A Pin Assignments .................................................................................10
Network Interface Card (NIC) Application ..........................................................18
MII Interface .......................................................................................................20
MII Data Interface ...............................................................................................21
Loopback Paths ..................................................................................................23
Repeater Block Diagram ....................................................................................24
MDIO Interrupt Signaling ....................................................................................25
Management Interface - Read Frame Structure .................................................25
Management Interface - Write Frame Structure .................................................25
LXT970A Initialization Sequence .......................................................................30
Auto-Negotiation Operation ................................................................................31
100BASE-TX Frame Structure ...........................................................................33
100BASE-TX Data Flow .....................................................................................33
LXT970A Protocol Sublayers .............................................................................36
100BASE-TX Reception with No Errors .............................................................37
100BASE-TX Reception with Invalid Symbol ....................................................37
100BASE-TX Transmission with No Errors .......................................................37
100BASE-TX Transmission with Collision .........................................................37
Voltage Divider ...................................................................................................45
Typical Interface Circuitry ...................................................................................46
MII - 100BASE-TX Receive Timing / 4B Mode ...................................................51
MII - 100BASE-TX Transmit Timing / 4B Mode .................................................52
MII - 100BASE-TX Receive Timing / 5B Mode ...................................................53
100BASE-TX Transmit Timing / 5B Mode ..........................................................54
MII - 100BASE-FX Receive Timing / 4B Mode ...................................................55
MII - 100BASE-FX Transmit Timing / 4B Mode ..................................................56
MII - 10BASE-T Receiving Timing ......................................................................57
MII - 10BASE-T Transmit Timing .......................................................................58
10BASE-T SQE (Heartbeat) Timing ...................................................................59
10BASE-T Jab and Unjab Timing ......................................................................59
Auto Negotiation and Fast Link Pulse Timing ....................................................60
Fast Link Pulse Timing .......................................................................................60
MDIO Timing when Sourced by STA .................................................................61
MDIO Timing when Sourced by PHY .................................................................61
Power-Down Recovery Timing (Over Recommended Range) ...........................62
PHY Identifier Bit Mapping .................................................................................66
64-Pin QFP Package Diagram ...........................................................................73
64-Pin TQFP Package Diagram .........................................................................74
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT970 | Fast Ethernet Transceiver |
| LXT970QC | Fast Ethernet Transceiver |
| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。