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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 32/74頁 |
| 文件大小： | 1061K |
| 代理商： | LXT970A |
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LXT970A
—
Dual-Speed Fast Ethernet Transceiver
32
Datasheet
2.5.2
Monitoring Status via Indicator Pins
The LEDS, LEDR, LEDT, LEDL, and LEDC pins are CMOS digital outputs that drive LEDs.
These pins along with the FDS/MDINT output, can also be used to externally monitor the status of
the LXT970A. The following notes apply to the FDS/MDINT and LED pins:
LEDR, LEDT and LEDC pulse Low to indicate receive, transmit, and collision activity
respectively. When the LXT970A asserts these signals, it automatically extends them for 100
ms.
LEDL indicates link status and LEDS indicates link speed. LEDL and LEDS are active Low.
In its default state (17.1 = 0), the MDINT/FDS output indicates duplex condition. FDS is
active High.
Table 16
shows the state of the LXT970A according to the status of LEDL, LEDS, and FDS pins.
2.6
100BASE-X Operation
2.6.1
100BASE-X MII Operations
The MAC exchanges data with the LXT970A over the MII interface. The LXT970A converts the
digital data from the MAC into an analog waveform that is transmitted to the network via the
copper (TX) or fiber (FX) interface. The LXT970A converts analog signals received from the
network into a digital format and sends them to the MAC via the MII. Refer to the MII interface
discussion on
page 20
for details on MII control and data signals.
The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However,
data is normally transmitted across the MII interface in 4-bit nibbles. The LXT970A incorporates a
4B/5B encoder/decoder circuit that translates 4-bit nibbles from the MII into 5-bit symbols for the
100BASE-X connection, and translates 5-bit symbols from the 100BASE-X connection into 4-bit
nibbles for the MII.
Figure 14
shows the data conversion flow from nibbles to symbols.
Table 17
shows 4B/5B symbol coding (not all symbols are valid).
In some applications it may be desirable to bypass the 4B/5B encoder/decoder circuit, and operate
the MII as a 5-bit symbol mode interface. The LXT970A provides additional lines in both the
receive and transmit channels (RXD4 & TXD4) to accommodate MACs that accept 5-bit symbols.
Table 16. LXT970A Status using FDS/LED Pins
LXT970A State
Pin Status
LEDL
LEDS
FDS
During Power-up
High
High
Low
During Auto-Negotiation or
Link Failure
High
High
Low
Link-up; 100 Mbps; full-duplex
Low
Low
High
Link-up; 100 Mbps; half-duplex
Low
Low
Low
Link-up; 10 Mbps; full-duplex
Low
High
High
Link-up; 10 Mbps; half-duplex
Low
High
Low
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相關(guān)代理商/技術(shù)參數(shù) |
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| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
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| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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