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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 28/74頁 |
| 文件大?。?/td> | 1061K |
| 代理商： | LXT970A |
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LXT970A
—
Dual-Speed Fast Ethernet Transceiver
28
Datasheet
2.3.2.1
Master Clock Mode
The Master Clock mode is recommended in most Network Interface Cards (NICs) and switch
applications. In Master Clock mode the LXT970A is the master clock source for data transmission,
and requires a 25 MHz reference signal at XI. The reference clock may be supplied either from a
crystal oscillator or from a digital clock circuit with the following specifications:
A frequency of 25 MHz +/-100 ppm
40/60 duty cycle or better
CMOS voltage levels (V
OH
>3.2V).
In Master Clock Mode, TX_CLK is an output and the LXT970A automatically sets the speed of
TX_CLK to match line conditions. If the line is operating at 100 Mbps, TX_CLK will be set to 25
MHz. If the line is operating at 10 Mbps, TX_CLK will be set to 2.5 MHz.
External Crystal
A crystal is typically used in NIC applications. If using a crystal oscillator, it should be
fundamental-mode and parallel-resonant, with a drive capacity of at least 7 pF. Attach between the
XI and XO pins. Add compensating capacitors between each leg and digital ground. The correct
value to use is the nominal drive capacity of the crystal minus 3 pF (input capacitance of the XI and
XO pins). One crystal can be used to drive two LXT970As. Connect the XO pin of only one 970
to one side of the crystal, and connect the other side to both XI pins. Calculate compensation
accordingly.
External Clock
An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications.
When a clock is supplied to XI, XO is left open.
TX Clock Advance Mode
When operating in Master Clock mode under MDIO Control, the user can advance the transmit
clock relative to TXD<4:0> and TX_ER. When TX_CLK Advance is selected, the LXT970A
clocks TXD data in on the falling edge of TX_CLK, instead of the rising edge.
This mode provides an increase in timing margins of TXD, relative to TX_CLK. TX_CLK
Advance is enabled when bit 19.5 = 1.
2.3.2.2
Slave Clock Mode
The Slave Clock mode is typically used for repeater applications, where the LXT970A is not the
master clock source for data transmissions. In Slave Clock Mode, a digital clock circuit with TTL
levels (V
OH
>2.4V) must supply the TX_CLK input. The frequency may be either 25 MHz or 2.5
MHz. Either frequency can be used during auto-negotiation. However, once link is established,
the supplied frequency must match the link state. A 25 MHz clock must be supplied for correct
operation of a 100TX or 100FX link, and a 2.5 MHz clock must be supplied for correct operation
of a 10BT link. In Slave Clock mode, XI is connected to ground and XO is left open.
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| LXT970 | Fast Ethernet Transceiver |
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| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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