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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 12/74頁 |
| 文件大?。?/td> | 1061K |
| 代理商： | LXT970A |
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LXT970A
—
Dual-Speed Fast Ethernet Transceiver
12
Datasheet
3
TRSTE
I
Tri-state
. In DTE Mode (19.13 = 0), when TRSTE input is High, the LXT970A
isolates itself from the MII Data Interface, and controls the MDIO register bit
0.10 (Isolate bit).
When MDDIS is High, TRSTE provides continuous control over bit 0.10. When
MDDIS is Low, TRSTE sets initial (default) values only and reverts control back
to the MDIO interface.
In Repeater Mode (19.13 = 1), when TRSTE input is High, the LXT970A tri-
states the receive outputs of the MII (RXD<4:0>, RX_DV, RX_ER, RX_CLK).
MII Control Interface Pins
15
MDDIS
I
Management Disable
. When MDDIS is High, the MDIO is restricted to Read
Only and the MF<4:0>, CFG<1:0>, and FDE pins provide continual control of
their respective bits. When MDDIS is Low at power up or Reset, the MF<4:0>,
CFG<1:0>, and FDE pins control only the initial or
“
default
”
values of their
respective register bits. After the power-up/reset cycle is complete, bit control
reverts to the MDIO serial channel.
45
MDC
I
Management Data Clock
. Clock for the MDIO serial data channel. Maximum
frequency is 2.5 MHz.
44
MDIO
I/O
Management Data Input/Output
. Bidirectional serial data channel for PHY/
STA communication.
2
FDS/MDINT
OD
Full-Duplex Status.
When bit 17.1 = 0 (default), this pin indicates full-duplex
status. (High = full-duplex, Low = half-duplex)
This pin can drive a high efficiency LED. (See
Table 23
for detail specifications).
Management Data Interrupt
. When bit 17.1 = 1, an active Low output on this
pin indicates status change.
Interrupt is cleared by sequentially reading Register 1, then Register 18.
Table 3. LXT970A Fiber Interface Signal Descriptions
Pin#
1
Pin Name
I/O
2
Signal Description
17
18
FIBOP
FIBON
O
Fiber Output, Positive and Negative
. Differential pseudo-ECL driver pair compatible with
standard fiber transceiver for 100BASE-FX.
27
28
FIBIP
FIBIN
I
Fiber Input, Positive and Negative
. Differential pseudo-ECL receive pair compatible with
standard fiber transceiver for 100BASE-FX.
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
Table 2. LXT970A MII Signal Descriptions (Continued)
Pin#
1
Pin Name
I/O
2,3
Signal Description
4
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
3. If bit 17.3 = 0, 55
series termination resistors are recommended on all output signals to avoid undershoot/overshoot, even
on short traces.
If bit 17.3 = 1, termination resistors are not required.
4. The LXT970A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an
“
X.Y
”
notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT970 | Fast Ethernet Transceiver |
| LXT970QC | Fast Ethernet Transceiver |
| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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