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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 64/74頁 |
| 文件大小： | 1061K |
| 代理商： | LXT970A |
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LXT970A
—
Dual-Speed Fast Ethernet Transceiver
64
Datasheet
Table 45. Control Register (Address 0)
Bit
Name
Description
Type
1
Default
0.15
Reset
1 = Reset chip.
0 = Enable normal operation.
R/W
SC
0
0.14
Loopback
1 = Enable loopback mode. When Loopback is enabled, during 100
Mbps operation, the LXT970A disconnects its transmitter and receiver
from the network. Data sent by the controller passes through the chip
and then gets looped back to the MII. During 10 Mbps operation the
preamble, SFD, and data loop directly back to the MII.
0 = Disable loopback mode.
R/W
0
0.13
Speed
Selection
1 = 100 Mbps
0 = 10 Mbps
R/W
Note 2
0.12
Auto-
Negotiation
Enable
1 = Enable auto-negotiate process (overrides speed select and duplex
mode bits).
0 = Disable auto-negotiate process.
R/W
Note 3
0.11
Power Down
1 = Enable power down.
0 = Enable normal operation.
R/W
Note 4
0.10
Isolate
1 = Electrically isolate LXT970A from MII.
0 = Normal operation.
R/W
Note 5
0.9
Restart Auto-
Negotiation
1 = Restart auto-negotiation process.
0 = Normal operation.
R/W
SC
Note 6
0.8
Duplex Mode
1 = Enable full-duplex.
0 = Enable half-duplex.
R/W
Note 7
0.7
Collision Test
1 = Enable COL signal test. Bit 0.14 must be enabled to use this bit.
This bit is used in conjunction with bit 0.14 to test the COL output.
0 = Disable COL signal test.
R/W
0 Note
8
0.6:4
Transceiver
Test Mode
Not Supported.
RO
0
0.3
Master-Slave
Enable
Not Supported.
RO
0
0.2
Master-Slave
Value
Not Supported.
RO
0
0.1:0
Reserved
R/W
0
1. R/W = Read/Write
SC = Self Clearing
2. If auto-negotiation is enabled, this bit is ignored. If auto-negotiation is disabled, the default value of bit 0.13 is determined by
pin CFG0.
3. The default value of bit 0.12 is determined by pin MF0.
4. The LXT970A internally maintains all set values of the configuration registers upon exiting power-down mode. A delay of 500
ns minimum is required from the time power down is cleared until any register can be written.
5. The default value of bit 0.10 is determined by pin TRSTE.
6. If auto-negotiation is enabled, the default value of bit 0.9 is determined by pin CFG0. If auto-negotiation is disabled, the
default value of
bit 0.9 = 0.
7. If auto-negotiation is enabled, this bit is ignored. If auto-negotiation is disabled, the default value of bit 0.8 is determined by
pin FDE.
8. This bit is ignored unless loopback is enabled (0.14 = 1).
相關PDF資料 |
PDF描述 |
|---|---|
| LXT970 | Fast Ethernet Transceiver |
| LXT970QC | Fast Ethernet Transceiver |
| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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