deveopmen
Watchdog Timer
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
108
System clock control register 0 (Note 1)
Symbol
CM0
Address
0006
16
When reset
0000 X000
2
Bit
Function
Bit symbol
b7
b6
b5
b4
b3 b2
b1
b0
3
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
0 : Do not stop peripheral clock
in wait mode
1 : Stop peripheral clock in
wait mode (Note 3)
b1 b0
CM07
CM05
CM04
CM01
CM02
CM00
Clock oname
select bit (Note 2)
WAIT peripheral
function clock stop bit
Port X
C
select bit
0 : I/O port
1 : X
CIN
-X
COUT
generation (Note 4)
0 : Main clock On
1 : Main clock Off (Note 6)
0 : Watchdog timer interrupt
1 : Reset (Note 7)
Main clock (X
IN
-X
OUT
)
stop bit (Note 5)
Watchdog timer
function select bit
System clock select bit
(Note 8)
0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
W
R
AA
AA
AA
AA
AA
AA
AA
CM06
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Set bit 0 of the protect register (address 000A
16
) to
“
1
”
before writing to this register.
Note 2: The port P5
3
dose not function as an I/O port in microprocessor or memory expansion
mode.
When outputting ALE to P5
3
(bits 5 and 4 of processor mode register 0 is "01"), set
these bits to "00".
The port P5
3
function is not selected, even when you set "00" in microprocessor or
memory expansion mode and bit 7 of the processor mode register 0 is "1".
Note 3: fc
32
is not included. When this bit is set to "1", PLL cannot be used in WAIT.
Note 4: When Xc
IN
-Xc
OUT
is used, set port P8
6
and P8
7
to no pull-up resistance with the input
port.
Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop
the main clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is
stable. Then set this bit to "1".
When X
IN
is used after returning from stop mode, set this bit to "0".
When this bit is "1", X
OUT
is "H". Also, the internal feedback resistance remains ON, so
X
IN
is pulled up to X
OUT
("H" level) via the feedback resistance.
Note 6: When the main clock is stopped, the main clock division register (address 000C
16
) is set
to the division by 8 mode.
However, in ring oscillator mode, the main clock division register is not set to the division
by 8 mode when X
IN
-X
OUT
is stopped by this bit.
Note 7: When "1" has been set once, "0" cannot be written by software.
Note 8: Set this bit "0" to "1" when sub clock oscillation is stable by setting CM04 to "1".
Set this bit "1" to "0" when main clock oscillation is stable by setting CM05 to "0".
Do not set CM04 and CM05 simultaneously.
Figure 1.10.3. System clock control register 0