SFR
deveopmen
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
41
Address
0180
16
0181
16
0182
16
0183
16
0184
16
0185
16
0186
16
0187
16
0188
16
0189
16
018A
16
018B
16
018C
16
018D
16
018E
16
018F
16
0190
16
Group 3 waveform generate control register 0
0191
16
Group 3 waveform generate control register 1
0192
16
Group 3 waveform generate control register 2
0193
16
Group 3 waveform generate control register 3
0194
16
Group 3 waveform generate control register 4
0195
16
Group 3 waveform generate control register 5
0196
16
Group 3 waveform generate control register 6
0197
16
Group 3 waveform generate control register 7
0198
16
Group 3 waveform generate mask register 4
0199
16
019A
16
Group 3 waveform generate mask register 5
019B
16
019C
16
Group 3 waveform generate mask register 6
019D
16
019E
16
Group 3 waveform generate mask register 7
019F
16
01A0
16
Group 3 base timer register
01A1
16
01A2
16
Group 3 base timer control register 0
01A3
16
Group 3 base timer control register 1
01A4
16
01A5
16
01A6
16
Group 3 function enable register
01A7
16
Group 3 RTP output buffer register
01A8
16
01A9
16
01AA
16
01AB
16
Group 3 high-speed HDLC communication control register 1
01AC
16
Group 3 high-speed HDLC communication control register
01AD
16
Group 3 high-speed HDLC communication register
HDLCF
01AE
16
Group 3 high-speed HDLC transmit counter
01AF
16
Register
Group 3 waveform generate register 0
G3PO0
Group 3 waveform generate register 1
G3PO1
Group 3 waveform generate register 2
G3PO2
Group 3 waveform generate register 3
G3PO3
Group 3 waveform generate register 4
G3PO4
Group 3 waveform generate register 5
G3PO5
Group 3 waveform generate register 6
G3PO6
Group 3 waveform generate register 7
G3PO7
G3POCR0
G3POCR1
G3POCR2
G3POCR3
G3POCR4
G3POCR5
G3POCR6
G3POCR7
G3MK4
G3MK5
G3MK6
G3MK7
G3BT
G3BCR0
G3BCR1
G3FE
G3RTP
HDLC1
HDLC
HDLCC
Address
01B0
16
01B1
16
01B2
16
01B3
16
01B4
16
01B5
16
01B6
16
01B7
16
01B8
16
01B9
16
01BA
16
01BB
16
01BC
16
01BD
16
01BE
16
01BF
16
01C0
16
01C1
16
01C2
16
01C3
16
01C4
16
01C5
16
01C6
16
01C7
16
01C8
16
01C9
16
01CA
16
01CB
16
01CC
16
01CD
16
01CE
16
01CF
16
01D0
16
01D1
16
01D2
16
01D3
16
01D4
16
A-D1 control register 2
01D5
16
01D6
16
A-D1 control register 0
01D7
16
A-D1 control register 1
01D8
16
01D9
16
01DA
16
01DB
16
01DC
16
01DD
16
01DE
16
01DF
16
Register
Group 3 high-speed HDLC data compare register 0
HDLCCP0
Group 3 high-speed HDLC data mask register 0
HDLCMK0
Group 3 high-speed HDLC data compare register1
HDLCCP1
Group 3 high-speed HDLC data mask register 1
HDLCMK1
Group 3 high-speed HDLC data compare register 2
HDLCCP2
Group 3 high-speed HDLC data mask register 2
HDLCMK2
Group 3 high-speed HDLC data compare register 3
HDLCCP3
Group 3 high-speed HDLC data mask register 3
HDLCMK3
A-D1 register 0
AD10
A-D1 register 1
AD11
A-D1 register 2
AD12
A-D1 register 3
AD13
A-D1 register 4
AD14
A-D1 register 5
AD15
A-D1 register 6
AD16
A-D1 register 7
AD17
AD1CON2
AD1CON0
AD1CON1
The blank area is reserved and cannot be used by user.