deveopmen
Timing (Vcc = 5V)
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
348
Timing requirements (referenced to V
CC
= 5V, V
SS
= 0V at Topr = 25
o
C unless otherwise specified)
Table 1.32.6. External clock input
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
26
26
30
0
0
0
0
25
Max.
External clock rise time
External clock fall time
ns
ns
t
r
t
f
Min.
33
13
13
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
ns
ns
ns
t
c
t
w(H)
t
w(L)
Parameter
Symbol
Unit
Standard
5
5
Min.
Data input setup time
RDY input setup time
HOLD input setup time
ns
ns
ns
t
su(DB-BCLK)
t
su(RDY-BCLK )
t
su(HOLD-BCLK )
Parameter
Symbol
Unit
Max.
Standard
Data input hold time
Data input hold time
ns
ns
t
h(RD-DB)
t
h(CAS -DB)
t
h(BCLK -RDY)
t
h(BCLK-HOLD )
t
d(BCLK-HLDA )
Note: Calculated according to the BCLK frequency as follows:
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
ns
ns
ns
RDY input hold time
HOLD input hold time
HLDA output delay time
Data input access time (RD standard, no wait)
Data input access time (AD standard, CS standard, no wait)
ns
ns
t
ac1(RD-DB)
t
ac1(AD-DB)
ns
ns
ns
ns
t
ac2(RD-DB)
t
ac2(AD-DB)
t
ac3(RD-DB)
t
ac3(AD-DB)
Data input access time (RD standard, with wait)
Data input access time (AD standard, CS standard, with wait)
Data input access time
(RD standard, when accessing multiplex bus area)
Data input access time
(AD standard, CS standard, when accessing
multiplex bus area)
Data input access time (RAS standard, DRAM access)
t
ac1(RD
–
DB)
=
f
(BCLK)
X 2
10
9
–
35
10
9
[ns]
t
ac2(RD
–
DB)
=
f
(BCLK)
X 2
–
35
10 X m
[ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
t
ac1(AD
–
DB)
=
f
(BCLK)
–
35
[ns]
t
ac2(AD
–
DB)
=
–
35
10 X n
f
(BCLK)
[ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
t
ac3(RD
–
DB)
=
f
(BCLK)
X 2
–
35
10 X m
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
t
ac3(AD
–
DB)
=
f
(BCLK)
X 2
–
35
10 X n
[ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
(Note)
(Note)
ns
ns
t
ac4(CAS-DB)
t
ac4(CAD-DB)
Data input access time (CAS standard, DRAM access)
Data input access time (CAD standard, DRAM access)
(Note)
ns
t
ac4(RAS-DB)
t
ac4(RAS
–
DB)
=
f
(BCLK)
X 2
–
35
10 X m
[ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
t
ac4(CAS
–
DB)
=
–
35
10 X n
f
(BCLK)
X 2
[ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
t
ac4(CAD
–
DB)
=
f
(BCLK)
–
35
10 X l
[ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
Table 1.32.7. Memory expansion and microprocessor modes
V
CC
= 5V