deveopmen
Rev.B2 for proof reading
Reset
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
28
(00B7
16
)
(00B8
16
)
(00B9
16
)
(00BA
16
)
(00BB
16
)
(00C0
16
)
(00C1
16
)
(00C2
16
)
(00C3
16
)
(00C4
16
)
(00C5
16
)
(00C6
16
)
(00C7
16
)
(00C8
16
)
(00C9
16
)
(00CA
16
)
(00CB
16
)
(00CC
16
)
(00CD
16
)
(00CE
16
)
(00CF
16
)
(00D0
16
)
(00D1
16
)
(00D4
16
)
(00D5
16
)
(00D8
16
)
(00D9
16
)
(00DA
16
)
(00DB
16
)
(00DC
16
)
(00DD
16
)
(00DE
16
)
(00DF
16
)
(0092
16
)
(0093
16
)
(0094
16
)
(0095
16
)
(0096
16
)
(0097
16
)
(0098
16
)
(0099
16
)
(009A
16
)
(009B
16
)
(009C
16
)
(009D
16
)
(009E
16
)
(009F
16
)
(00A0
16
)
(00A1
16
)
(00A2
16
)
(00A3
16
)
(00A4
16
)
(00A5
16
)
(00A6
16
)
(00A7
16
)
(00A8
16
)
(00A9
16
)
(00AA
16
)
(00AB
16
)
(00B0
16
)
(00B1
16
)
(00B2
16
)
(00B3
16
)
(00B4
16
)
(00B5
16
)
(00B6
16
)
UART1 transmit/NACK interrupt control register
Key input interrupt control register
Timer B0 interrupt control register
Intelligent I/O interrupt control register 1
Timer B2 interrupt control register
Intelligent I/O interrupt control register 3
Timer B4 interrupt control register
Intelligent I/O interrupt control register 5
INT4 interrupt control register
Intelligent I/O interrupt control register 7
INT2 interrupt control register
INT0 interrupt control register
Exit priority register
Interrupt request register 0
Interrupt request register 1
Interrupt request register 2
Interrupt request register 3
Interrupt request register 4
Interrupt request register 5
Interrupt request register 6
Interrupt request register 7
Interrupt request register 8
Interrupt request register 9
Interrupt request register 10
Interrupt request register 11
Interrupt enable register 0
Interrupt enable register 1
Interrupt enable register 2
Interrupt enable register 3
Interrupt enable register 4
Interrupt enable register 5
Interrupt enable register 6
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
(67)
(68)
(69)
(70)
(71)
(72)
(73)
(74)
(75)
(76)
(77)
(78)
(79)
(80)
(81)
(82)
(83)
(84)
(85)
(86)
(87)
(88)
(89)
(90)
(91)
(92)
(93)
(94)
(95)
(96)
(97)
(98)
(99)
(100)
(101)
(102)
(103)
(104)
(105)
(106)
(107)
(108)
(109)
(110)
(111)
(112)
(113)
(114)
(115)
(116)
Interrupt enable register 7
Interrupt enable register 8
Interrupt enable register 9
Interrupt enable register 10
Interrupt enable register 11
Group 0 time measurement/waveform
generate register 0
Group 0 time measurement/waveform
generate register 1
Group 0 time measurement/waveform
generate register 2
Group 0 time measurement/waveform
generate register 3
Group 0 time measurement/waveform
generate register 4
Group 0 time measurement/waveform
generate register 5
Group 0 time measurement/waveform
generate register 6
Group 0 time measurement/waveform
generate register 7
Group 0 waveform generate control register 0
Group 0 waveform generate control register 1
Group 0 waveform generate control register 4
Group 0 waveform generate control register 5
Group 0 time measurement control register 0
Group 0 time measurement control register 1
Group 0 time measurement control register 2
Group 0 time measurement control register 3
Group 0 time measurement control register 4
Group 0 time measurement control register 5
Group 0 time measurement control register 6
Group 0 time measurement control register 7
XXXX 0 0 0
XXXX 0 0 0
XX00 0 0 0
XX00 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XX00 0 0 0
XX0X00 0 0
0X00X0 0 0
0XX000 0 0
00X000 0 0
0XXX00 0 0
0XXX00 0 0
0XX000 0 0
0X00X0 0 0
0X00X0 0 0
0X00X0 0 0
00
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
x : Nothing is mapped to this bit
: Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
XX00X00X
XX000 00X
00X0 0 00X
XXX00 00X
00X 0 0 00X
XX00X00X
XX00X0XX
XXX00 00X
0XX00 00X
0XX0 0 00X
0XX00 00X
0XX00 00X
XX00X000
XX00X000
XX00X0X0
XX000000
00X00000
XXX00000
XXX00000
Intelligent I/O interrupt control register 9/
CAN interrupt 0 control register
Figure 1.4.3. Device's internal status after a reset is cleared (2/10)