deveopmen
Rev.B2 for proof reading
Usage precaution
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
338
V
C
C (3.0pF)
V
IN
Internal circuit of microprocessor
Sensor-equivalent circuit
R (7.8k )
R
0
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D con-
verter turns out to be approximately 3.0 k
. Tables 1.31.1 and 1.31.2 show output impedance values
based on the LSB values.
Figure 1.31.1 A circuit equivalent to the A-D conversion terminal
(7) After A-D conversion is complete, if the CPU reads the A-D register at the same time as the A-D
conversion result is being saved to A-D register, wrong A-D conversion value is saved into the A-D
register. This happens when the internal CPU clock is selected from divided main clock or sub-clock.
When using the one-shot or single sweep mode
Confirm that A-D conversion is complete before reading the A-D register.
(Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.)
When using the repeat mode or repeat sweep mode 0 or 1
Use the undivided main clock as the internal CPU clock.
Interrupts
(1) Setting the stack pointer
The value of the stack pointer is initialized to 000000
16
immediately after reset. Accepting an
interrupt before setting a value in the stack pointer may cause runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Regard-
ing the first instruction immediately after reset, generating any interrupts including the NMI inter-
rupt is prohibited.
Set an even address to the stack pointer so that operating efficiency is increased.
(2) The NMI interrupt
As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the V
CC
pin via a
resistance (pulled-up) if unused.
The NMI pin also serves as P8
5
, which is exclusively input. Reading the contents of the P8
register allows reading the pin value. Use the reading of this pin only for establishing the pin level
at the time when the NMI interrupt is input.
Signal of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for NMI
pin.