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Intelligent I/O (Serial I/O)
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
270
Interrupt request
generation timing
Clock synchronous serial I/O mode (group 0 and 1)
Table 1.23.12 gives specifications for the clock synchronous serial I/O mode.
Table 1.23.12. Specifications of clock synchronous serial I/O mode (group 0 and 1)
Item
Transfer data format
Transfer clock
Specification
Transfer data length:
When internal clock is selected
_
Transfer speed is determined when the base timer is reset by the ch0 WG function
Transfer rate (bps) = base timer count source (frequency) / (k+2) / 2
k : values set to WG register 0
_
Transfer clock is generated when the transfer clock in the phase delayed
waveform output mode
Transmit clock : ch3 WG function
Receive clock : ch2 WG function
Sets the same value in the WG registers on ch2 and ch3
When external clock is selected
_
Transfer rate (bps) = Clock input to ISCLK pin
Transmission start condition To start transmission, the following requirements must be met:
Transmit enable bit =
“
1
”
Write data to transmit buffer
Reception start condition
To start reception, the following requirements must be met:
Receive enable bit =
“
1
”
When transmitting
_
When transmit buffer is empty, transmit interrupt cause select bit =
“
0
”
_
When transmission is completed,
transmit interrupt cause select bit =
“
1
”
When receiving
When data is transferred to SI/O receive buffer register
Error detection
Overrun error
This error occurs when the next data is ready before the contents of SI/O receive
buffer register are read out
Select function
LSB first/MSB first selection
When transmission/reception begins with bit 0 or bit 7, it can be selected
Transmit/receive data polarity switching
This function is reversing ISTxD pin output and ISRxD pin input.
(All I/O data level is reversed.)
8 bits fixed
Note: Set the transmission clock to at least 6 divisions of the base timer clock.
Table 1.23.13 lists I/O pin functions for the clock synchronous serial I/O mode of groups 0 and 1.
From when the operating mode is selected until transmission starts, the ISTxDi pin is "H" level. Figure
1.23.31 shows typical transmit/receive timings in clock synchronous serial I/O mode in group 0 and 1.