deveopmen
Clock synchronous serial I/O mode
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
179
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
T
CLK
Stopped pulsing because transfer enable bit =
“
0
”
Data is set in UARTi transmit buffer register
Tc = TCLK = 2(m + 1) / fi
fi: frequency of BRGi count source (f
1
, f
8
, f
2n
)
m: value set to BRGi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
“
H
”
“
L
”
“
0
”
“
1
”
“
0
”
“
1
”
“
0
”
“
1
”
CTSi
The above timing applies to the following settings:
Internal clock is selected.
CTS function is selected.
CLK polarity select bit =
“
0
”
.
Transmit interrupt cause select bit =
“
0
”
.
Transmit interrupt
request bit (IR)
“
0
”
“
1
”
Stopped pulsing because CTS =
“
H
”
Transferred from UARTi transmit buffer register to UARTi transmit register
Shown in ( ) are bit symbols.
Cleared to
“
0
”
when interrupt request is accepted, or cleared by software
Dummy data is set in UARTi transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
RTSi
“
H
”
“
L
”
“
0
”
“
1
”
“
0
”
“
1
”
“
0
”
“
1
”
Receive enable
bit (RE)
“
0
”
“
1
”
Receive data is taken in
Transferred from UARTi transmit buffer register to UARTi transmit register
Read out from UARTi receive buffer register
The above timing applies to the following settings:
External clock is selected.
RTS function is selected.
CLK polarity select bit =
“
0
”
.
f
EXT
: frequency of external clock
Transferred from UARTi receive register
to UARTi receive buffer register
Receive interrupt
request bit (IR)
“
0
”
“
1
”
Shown in ( ) are bit symbols.
The following conditions are met when the CLKi
input before data reception =
“
H
”
Transmit enable bit
“
1
”
Receive enable bit
“
1
”
Dummy data write to UARTi transmit buffer register
Cleared to
“
0
”
when interrupt request is accepted, or cleared by software
1 / f
EXT
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
0
D
1
D
2
D
3
D
4
D
5
D
7
D
6
Over run error
flag(OER)
D
“
0
”
“
1
”
Example of transmit timing (when internal clock is selected)
Example of receive timing (when external clock is selected)
Figure 1.18.1. Typical transmit/receive timings in clock synchronous serial I/O mode