deveopmen
CPU Rewrite Mode (Flash Memory Version)
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
385
Flash memory control register 0
Symbol
FMR0
Address
0057
16
When reset
XX000001
2
R
b7
b6
b5
b4
b3
b2 b1
b0
FMR00
Bit symbol
Bit name
Function
RW
0: Busy (being written or erased)
1: Ready
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
FMR01
0: Boot ROM area is accessed
1: User ROM area is accessed
Lock bit disable bit
(Note 2)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
Flash memory reset bit
(Note 3)
0: Normal operation
1: Reset
User ROM area select bit (
Note 4) (Effective in only
boot mode)
FMR02
FMR03
FMR05
0
Note 1: For this bit to be set to
“
1
”
, the user needs to write a
“
0
”
and then a
“
1
”
to it in
succession. When it is not this procedure, it is not enacted in
“
1
”
. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit. Also write to this
bit when NMI pin is "H" level.
Note 2: For this bit to be set to
“
1
”
, the user needs to write a
“
0
”
and then a
“
1
”
to it in succession
when the CPU rewrite mode select bit =
“
1
”
. When it is not this procedure, it is not
enacted in
“
1
”
. This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently
after setting it to 1 (reset).
Note 4: Use the control program except in the internal flash memory for write to this bit.
AA
A
AA
AA
AA
AA
AA
RY/BY signal status bit
Reserved bit
Must always be set to
“
0
”
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Figure 1.34.1. Flash memory control register
Flash memory control register (address 0057
16
Bit 0 of the flash memory control register 0 is the RY/BY signal status bit used exclusively to read the
operating status of the flash memory. During programming and erase operations, it is
“
0
”
. Otherwise, it is
“
1
”
.
Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to
“
1
”
, so that software commands become acceptable. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other
than the internal flash memory. To set this bit to
“
1
”
, it is necessary to write
“
0
”
and then write
“
1
”
in
succession when NMI pin is "H" level. The bit can be set to
“
0
”
by only writing a
“
0
”
.