DMAC II
deveopmen
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
121
Causes to activate DMAC II
Transfer data
Unit of transfer
Direction of transfer
Transfer space
Transfer mode
Chained transfer function
Interrupt at end of transfer
Multiple transfer function
Interrupt request from any peripheral I/O whose interrupt priority is set to
"level 7" by the Interrupt Control Register
(1) Memory -> memory (memory-to-memory transfer)
(2) Immediate data -> memory (immediate data transfer)
(3) Memory (or immediate data) + memory -> memory (arithmetic transfer)
Transferred in 8 or 16 bits
64-Kbyte space at address up to 0FFFF
16
Fixed or forward address
Can be selected individually for the source and the destination of transfer.
(1) Single transfer
(2) Burst transfer
Parameters (transfer count, transfer address, and other information)
are switched over when the transfer counter reaches zero.
Interrupt is generated when the transfer counter reaches zero.
Multiple data transfers can be performed by one DMA II transfer request generated.
Item
Specification
(Note)
DMAC II
When requested by an interrupt from any peripheral I/O, the DMAC performs a memory-to-memory trans-
fer, an immediate data transfer, or an arithmetic transfer (to transfer the sum of two data added).
Specifications of DMAC II are shown in Table 1.12.1.
Table 1.12.1 Specifications of DMAC II
Note : When transfer unit is 16 bits and destination address is 0FFFF
16
, data is transfered to addresses
0FFFF
16
and 10000
16
. When source address is 0FFFF
16
, data is transfered as in the previous.
Settings of DMAC II
DMAC II can be enabled for use by setting up the following registers and tables.
Exit Priority Register (address 009F
16
)
DMAC II Index
Interrupt Control Register for the peripheral I/O that requests a transfer by DMAC II
Relocatable Vector Table for the peripheral I/O that requests a transfer by DMAC II
When using an intelligent I/O or CAN interrupt, Interrupt Enable Register
’
s interrupt request latch bit
(bit 0)
(1) Exit priority register (address 009F
16
)
If this register
’
s DMAC II select bit (bit 5) and fast interrupt select bit (bit 3) respectively are set to 1 and
0, DMAC II is activated by an interrupt request from any peripheral I/O whose interrupt priority is set to
“
level 7
”
by the interrupt priority level select bit.
The configuration of the exit priority register is shown in Figure 1.12.1.