Clock asynchronous serial I/O (UART) mode
deveopmen
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
182
Item
Specification
Transfer data format
Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
Start bit: 1 bit
Parity bit: Odd, even, or nothing as selected
Stop bit: 1 bit or 2 bits as selected
When internal clock is selected (bit 3 at addresses 0368
16
, 02E8
16
, 0338
16
, 0328
16
,
02F8
16
=
“
0
”
) : fi/16(m+1) (Note 1)
fi = f
1
, f
8
, f
2n
When external clock is selected (bit 3 at addresses 0368
16
, 02E8
16
, 0338
16
, 0328
16
,
02F8
16
=
“
1
”
) : f
EXT
/16(m+1)
(Note 1, 2)
CTS function, RTS function, CTS/RTS function chosen to be invalid
To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 036D
16
, 02ED
16
, 033D
16
, 032D
16
, 02FD
16
) =
“
1
”
- Transmit buffer empty flag (bit 1 at addresses 036D
16
, 02ED
16
, 033D
16
, 032D
16
,
02FD
16
) =
“
0
”
- When CTS function selected, CTS input level =
“
L
”
-
TxD output is selected by the corresponding peripheral function select register A, B
and C.
To start reception, the following requirements must be met:
Transfer clock
Transmission/reception control
Transmission start condition
Reception start condition
- Receive enable bit (bit 2 at addresses 036D
16
, 02ED
16
, 033D
16
, 032D
16
, 02FD
16
) =
“
1
”
- Start bit detection
When transmitting
- Transmit interrupt cause select bits (bit 4 at address 036D
16
, 02ED
16
, 033D
16
,
032D
16
, 02FD
16
) =
“
0
”
: Interrupts requested when data transfer from UARTi transfer
buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bit 4 at address 036D
16
, 02ED
16
, 033D
16
,
032D
16
, 02FD
16
) =
“
1
”
: Interrupts requested when data transmission from UARTi
transfer register is completed
When receiving
- Interrupts requested when data transfer from UARTi receive register to UARTi
receive buffer register is completed
Overrun error
(Note 3)
This error occurs when the next data is started to receive and 6.5 transfer
clock is elapsed before UARTi receive buffer register are read out.
Interrupt request
generation timing
Error detection
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.19.1 and 1.19.2 list the specifications of the UART mode. Figure 1.19.1 shows the
UARTi transmit/receive mode register.
Table 1.19.1. Specifications of UART Mode (1/2)
Note 1:
‘
m
’
denotes the value 00
16
to FF
16
that is set to the UARTi bit rate generator.
Note 2: f
EXT
is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will be over written with the next data.