deveopmen
Rev.B2 for proof reading
DMAC
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
118
Memory expansion mode
Microprocessor mode
No. of read No. of write
cycles
1
1
1
1
1
2
2
2
Single-chip mode
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.11.2. No. of DMAC transfer cycles
Transfer unit
Bus width
Access address
No. of read
cycles
1
1
—
—
1
2
—
—
No. of write
cycles
1
1
—
—
1
2
—
—
cycles
1
1
1
1
1
2
2
2
16-bit
(DSi =
“
1
”
)
8-bit
(DSi =
“
0
”
)
16-bit
(DSi =
“
1
”
)
8-bit
(DSi =
“
0
”
)
Even
Odd
Even
Odd
Even
Odd
Even
Odd
8-bit transfers
(BWi =
“
0
”
)
16-bit transfers
(BWi =
“
1
”
)
Coefficient j, k
Internal memory
External memory
Coefficient j Coefficient k
Internal ROM/RAM
No wait
Internal ROM/RAM
One wait
SFR area
Separate bus
No wait
Separate bus
One wait
Separate bus
Two waits
Separate bus
Three waits
Multiplex bus
1
2
2
1
2
3
4
3
1
2
2
2
2
3
4
3
DMA Request Bit
The DMAC can issue DMA requests using preselected DMA request factors for each channel as triggers.
The DMA transfer request factors include the reception of DMA request signals from the internal periph-
eral functions, software DMA factors generated by the program, and external factors using input from
external interrupt signals.
See the description of the DMAi factor selection register for details of how to select DMA request factors.
DMA requests are received as DMA requests when the DMAi request bit is set to
“
1
”
and the channel i
transfer mode select bits are
“
01
”
or
“
11
”
. Therefore, even if the DMAi request bit is
“
1
”
, no DMA request
is received if the channel i transfer mode select bit is
“
00
”
. In this case, DMAi request bit is cleared.
Because the channel i transfer mode select bits default to
“
00
”
after a reset, remember to set the channel
i transfer mode select bit for the channel to be activated after setting the DMAC related registers. This
enables receipt of the DMA requests for that channel, and DMA transfers are then performed when the
DMAi request bit is set.
The following describes when the DMAi request bit is set and cleared.