CAN Module
deveopmen
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
215
CAN0 slot interrupt mask register
b15
(b7)
(b0)
Symbol
C0SIMKR
Address
0211
16,
0210
16
When reset (Note)
0000
16
R W
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
SIM15
SIM14
SIM13
SIM12
SIM11
SIM10
Slot 15 interrupt
request mask bit
SIM9
SIM8
SIM7
SIM6
SIM5
Slot 14 interrupt
request mask bit
Slot 13 interrupt
request mask bit
Slot 12 interrupt
request mask bit
Slot 11 interrupt
request mask bit
Slot 10 interrupt
request mask bit
Slot 9 interrupt
request mask bit
Slot 8 interrupt
request mask bit
Slot 7 interrupt
request mask bit
Slot 6 interrupt
request mask bit
Slot 5 interrupt
request mask bit
Slot 4 interrupt
request mask bit
Slot 3 interrupt
request mask bit
Slot 2 interrupt
request mask bit
Slot 1 interrupt
request mask bit
Slot 0 interrupt
request mask bit
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
SIM4
SIM3
SIM2
SIM1
SIM0
Bit name
Function
Bit
symbol
b7
b0
b8
Figure 1.22.14. CAN0 slot interrupt mask register
12. CAN0 slot interrupt mask register
This register controls CAN interrupts by enabling or disabling interrupt requests generated by each
corresponding slot at completion of transmission or reception. Setting any bit of this register (SIMn
where n = 0
–
15) to 1 enables the interrupt request to be generated by the corresponding slot at
completion of transmission or reception.