deveopmen
Three-phase motor control timers
’
functions
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
160
Figure 1.16.6 shows the block diagram for three-phase waveform mode. The Low active output polarity
in three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W phase) and
negative waveforms (U phase, V phase, and W phase), six waveforms in total, are output from P8
0
, P8
1
,
P7
2
, P7
3
, P7
4
, and P7
5
as active on the
“
L
”
level. Of the timers used in this mode, timer A4 controls the
U phase and U phase, timer A1 controls the V phase and V phase, and timer A2 controls the W phase
and W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1,
and A2.
In outputting a waveform, dead time can be set so as to cause the
“
L
”
level of the positive waveform
output (U phase, V phase, and W phase) not to lap over the
“
L
”
level of the negative waveform output (U
phase, V phase, and W phase).
To set short circuit time, use three 8-bit timers, sharing the reload register, for setting dead time. A value
from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead
time works as a one-shot timer. If a value is written to the dead timer (030C
16
), the value is written to the
reload register shared by the three timers for setting dead time.
Any of the timers for setting dead time takes the value of the reload register into its counter, if a start
trigger comes from its corresponding timer, and performs a down count in line with the clock source
selected by the dead time timer count source select bit (bit 2 at 0309
16
). The timer can receive another
trigger again before the workings due to the previous trigger are completed. In this instance, the timer
performs a down count from the reload register
’
s content after its transfer, provoked by the trigger, to the
timer for setting dead time.
Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger
comes; it stops outputting pulses as soon as its content becomes 00
16
, and waits for the next trigger to
come.
The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V
phase, and W phase) in three-phase waveform mode are output, from respective ports by means of
setting
“
1
”
in the output control bit (bit 3 at 0308
16
). Setting
“
0
”
in this bit causes the ports to be the high-
impedance state. This bit can be set to
“
0
”
not only by use of the applicable instruction, but by entering
a falling edge in the NMI terminal or by resetting. Also, if
“
1
”
is set in the positive and negative phases
16
) causes one of the pairs of U phase and
___
___
___
“
L
”
, as a result, the output
control bit becomes the high-impedance state.