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CHAPTER 8 I/O PORTS
8.5.2
Operation of Port 2
This section describes the operation of port 2.
s Operation of Port 2
r Setting Port 2 as an output port in the Port 2 direction register (DDR2)
The value stored in the Port 2 data register (PDR2) is output to the Port 2 pin.
If the PDR2 register is read, the value stored in PDR2 register is output.
r Setting Port 2 as an input port in the Port 2 direction register (DDR2)
The Port 2 pin has high impedance.
If the Port 2 data register (PDR2) is set to a value, the value stored in the PDR2 register is
retained but not output to the pin.
If the PDR2 register is read, the pin input level ("0" for "L" or "1" for "H") is output.
Note:
If a read-modify-write instruction (such as the bit set instruction) is used to access the PDR2
register, no bit specified for output in the DDR2 register is affected. For a bit specified for
input in the DDR2 register, however, the pin input level is written to the PDR2 register.
Therefore, to change a bit specified for input to output, first set an output value to the PDR2
register and then specify the DDR2 register as an output port.
r Port operation after a reset
When the CPU is reset, the DDR2 register is initialized to "00H" and the Port 2 pin has high
impedance.
The PDR2 register is not initialized when the CPU is reset. To use the PDR2 as an output
port, first write an output value to the PDR2 register and then specify the DDR2 register as
an output port.
r Port operation in stop or time-base timer mode
If the port switches to stop mode or timebase timer mode while the pin status setting bit (SPL) of
the low power consumption mode control register (LPMCR) is set to "1", the pins come to have
high impedance regardless of the value in the Port 2 direction register (DDR2). Note that the
input buffer is forcibly shut off to prevent leakage due to an open circuit.