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11.6 Operation of the 16-Bit Reload Timer
s Counter Operating Status
The 16-bit down counter status is determined by the count enable bit (CNTE) values of the timer
control status register (TMCSR) and the internal trigger wait signal value (WAIT).
Figure 11.6-3"Counter Status Transition" shows the relationship between the count enable bit (CNTE) values
and the internal trigger wait signal (WAIT) values in the stop status (STOP status), trigger wait
status (WAIT status), and running status (RUN status)
Figure 11.6-3 Counter Status Transition
Reset
CNTE = "0"
Loading ends.
UF = "1"
RELD = "0"
(Single-shot mode)
TRG = "1"
(Software trigger)
External trigger from TIN
TRG = "1"
(Software trigger)
UF = "1"
RELD = "1"
(Reload mode)
CNTE = "1"
TRG = "0"
CNTE = "1"
TRG = "1"
STOP
CNTE = "0", WAIT = "1"
TO: I/O port
Counter: The counter value is retained
when the counter stops.
Immediately after a reset,
it is undefined.
TIN: Input disabled
WAIT
: State transition by hardware
: State transition by register access
: Wait signal (internal signal)
: Software trigger bit of timer control status register (TMCSR)
: Count enable bit of timer control status register (TMCSR)
: Underflow interrupt request flag bit of timer control status register (TMCSR)
: Reload selection bit of timer control status register (TMCSR)
LOAD
CNTE = "1", WAIT = "1"
CNTE = "1", WAIT = "0"
TO: Output initial value
Counter: The counter value is retained
when the counter stops.
Immediately after a reset,
it is undefined and remains so
until a value is loaded.
TIN: Only trigger input enabled
The contents of the reload register are
loaded into the counter
RUN
CNTE = "1", WAIT = "0"
TO: Functions as TO
Counter: Run
TIN: Functions as TIN
WAIT
TRG
CNTE
UF
RELD