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CHAPTER 6 INTERRUPTS
6.6.3
Operation of the Extended Intelligent I/O Service (EI2OS)
The CPU uses EI2OS to transfer data if a peripheral function (resource) outputs an
interrupt request while the corresponding interrupt control register (ICR) is set to
enable the activation of EI2OS. When the EI2OS processing terminates, the hardware
interrupt processing is performed.
s Operation Flow of the Extended Intelligent I/O Service (EI2OS)
Figure 6.6-7 Flow of Extended Intelligent I/O Service (El2OS) Operation
Data indicated by I/OA
(data transfer)
memory indicated by BAP
(-1)
Updage value
by BW
Updage value
by BW
NO
YES
EI2OS termination processing
Interrupt request
generated by peripheral
function
Termination
request from peripheral
function
ISE="1"
Read ISD/ISCS
Clear interrupt request from
the peripheral function
Return to CPU operation
Decrement DCT
Set S1 and S0 to "00B"
DIR="1"
IF="0"
BF="0"
DCT="00B"
Data indicated by BAP
(data transfer)
memory indicated by I/OA
Interrupt sequence
Clear ISE to "0"
Interrupt sequence
Update BAP
Update I/OA
Set S1 and S0 to "11B"
Set S1 and S0 to "01B"
SE="1"
ISD
: EIOS descriptor
ISCS : EIOS status register
IF
: IOA update/fixed selection bit inte EIOS status register (ISCS)
BW
: Transfer data length specification bit in the EIOS status register (ISCS)
BF
: BAP update/fixed selection bit in the EIOS status register (ISCS)
DIR
: Data transfer direction specification bit in the EIOS status register (ISCS)
SE
: EIOS termination control bit in the EIOS status register (ISCS)
DCT
: Data counter
I/OA
: I/O register address pointer
BAP
: Buffer address pointer
ISE
: EIOS enable bit in the interrupt controlregister (ICR)
S1, S0: EIOS status in the interrupt control register (ICR)