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4.3 Clock Selection Register (CKSCR)
Table 4.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR)
Bit name
Function
bit 15
bit 11
RESV:
Reserved bit
Always set "1".
bit 14
MCM:
Machine clock
indication bit
This bit indicates whether the main clock or a PLL clock has been
selected as the machine clock.
When this bit is set to "0", a PLL clock has been selected.
When this bit is set to "1", the main clock has been selected.
If the machine clock selection bit (MCS) is set to "0" and MCM is set to
"1", the PLL clock oscillation stabilization wait interval is in effect.
bit 13
bit 12
WS1, WS0:
Oscillation
stabilization wait
interval selection
bits
These bits select the oscillation stabilization wait interval for the
oscillation clock after the stop mode has been cleared due to an external
interrupt.
A reset cause initializes these bits to "11B".
Specify an oscillation stabilization wait interval appropriate for the
oscillator used.
bit 10
MCS:
Machine clock
selection bit
This bit specifies whether the main clock or a PLL clock is selected as
the machine clock.
When this bit is set to "0", a PLL clock is selected.
When this bit is set to "1", the main clock is selected.
If this bit has been set to "1" and is reset to "0", the oscillation
stabilization wait interval for the PLL clock starts. As a result, the time-
base timer counter and the interrupt request flag bit (TBOF) of the time-
base timer counter control register (TBTC) are cleared to "0".
For PLL clocks, the oscillation stabilization wait interval is fixed to 214/
HCLK. The oscillation stabilization wait interval is about 4.1 ms if the
oscillation clock frequency is 4 MHz.)
When the main clock has been selected, the oscillation clock divided by
2 is used as the machine clock. The machine clock frequency is 2 MHz
if the oscillation clock frequency is 4 MHz.
A reset initializes this bit to 1.
Note:
The MCS bit set to "1" can be reset to "0" while the interrupt request
enable bit (TBIE) of the time-base timer counter control register (TBTC)
or the interrupt level mask register (ILM) are set to disable timer-base
timer interrupt requests.
bit 9
bit 8
CS1, CS0:
Multiplier
selection bits
These bits select a PLL clock multiplier.
One of the four multipliers can be selected.
A reset initializes these bits to "00B".
Note:
These bits cannot be set while the machine clock selection bit (MCS) or
the machine clock indication bit (MCM) is set to "0". Set these bits only
after setting the MCS bit to "1".
HCLK: Oscillation clock frequency