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CHAPTER 6 INTERRUPTS
s Hardware Interrupt Structure
The four mechanisms (seven locations) shown in
Table 6.4-1 "Mechanisms Used for Hardware
Interrupts" are used for hardware interrupts. These four mechanisms (seven locations) must be
configured in a user program before hardware interrupts can be used.
s Hardware Interrupt Disable
Acceptance of a hardware interrupt request is disabled under the following conditions:
r Hardware interrupt acceptance disable during writing to the peripheral function (resource)
control register
No hardware interrupt request is accepted while data is written to the peripheral function
(resource) control register.
Figure 6.4-1 Hardware Interrupt Request While Writing to the Peripheral Function (Resource) Control
Register Area
Table 6.4-1 Mechanisms Used for Hardware Interrupts
Mechanism
Function
Peripheral function
Interrupt enable bit, interrupt
request bit
Controls interrupt requests from a peripheral
function (resource)
Interrupt controller
Interrupt control register (ICR)
Sets the interrupt level and controls EI2OS
CPU
Interrupt enable flag (I)
Identifies the interrupt enable status
Interrupt level mask register
(ILM)
Compares the request interrupt level and current
interrupt level
Microcode
Executes the interrupt processing routine
FFFC00H to
FFFFFFH in memory
Interrupt vector table
Stores the branch destination address for interrupt
processing
MOV A, #08
MOV io,A
MOV A,2000H
Interrupt processing
. . . . .
Instruction that writes to the peripheral function (resource) control register area
An interrupt request
is generated here
Does not branch
to the interrupt
Branches to
the interrupt
io: Peripheral function (resource) control register address