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型號(hào)：	MB90V560CR
廠商：	FUJITSU LTD
元件分類：	微控制器/微處理器
英文描述：	16-BIT, 8 MHz, MICROCONTROLLER, CPGA256
封裝：	PGA-256
文件頁(yè)數(shù)：	153/616頁(yè)
文件大?。?/td>	15240K
代理商：	MB90V560CR

CHAPTER 9 TIMEBASE TIMER

Usage Notes on the Timebase Timer

This section provides notes on how clearing of an interrupt request or clearing of the

timebase timer counter affects the functions.

s Timebase Timer Usage Notes

r Clearing interrupt requests

Clear the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) to "0"

while the interrupt request enable bit (TBIE) or the interrupt level mask register (ILM) of the

processor status (PS) is set to disabled.

r Functions affected by clearing of the timebase timer counter

Interval timer function (interval interrupt)

When the watchdog timer is being used

r Use of the timebase timer as the oscillation settling time timer

In stop mode in which the operating clock stops, the timebase timer counter is cleared and

stopped. When the timebase timer counter is cleared, the clock supplied from it starts to be

supplied again from the initial state. As a result, the H level may be shortened or the L level

may be prolonged by half a cycle at the maximum. Although the clock for the watchdog timer

also starts to be supplied again from the initial state, the watchdog timer operates in normal

cycles because the watchdog timer counter is cleared at the same time.

r Notes on peripheral functions to which clocks are supplied from the timebase timer

At power-on or in stop mode, the source oscillation is stopped.

Thus, the timebase timer

counter places the oscillation stabilization interval for the operating clock using the clock

supplied from the oscillator.

Depending on the oscillator type, an appropriate oscillation

stabilization interval must be specified.

For more information, see Section 4.5 "Oscillation Stabilization Wait Interval".

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