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CHAPTER 4 CLOCKS
4.4
Clock Mode
Two clock modes are provided: main clock mode and PLL clock mode.
s Main Clock Mode and PLL Clock Mode
r Main clock mode
In main clock mode, the main clock is used as the machine clock of the CPU and peripheral
functions (resources) while the PLL clocks are disabled.
r PLL clock mode
In PLL clock mode, a PLL clock is used as the machine clock of the CPU and peripheral
functions (resources). Specify a PLL clock multiplier in the multiplier selection bits (CS1 and
CS0) of the clock selection register (CKSCR).
s Clock Mode Transition
Setting the machine clock selection bit (MCS) of the clock selection register (CKSCR) causes
switching between main clock mode and PLL clock mode.
r Switching from main clock mode to PLL clock mode
When the MCS bit of the CKSCR that is set to "1" is reset to "0", switching from the main clock
to a PLL clock occurs after the PLL clock oscillation stabilization wait interval (214/HCLK) has
elapsed.
r Switching from PLL clock mode to main clock mode
When the MCS bit of the CKSCR that is set to "0" is reset to "1", switching from a PLL clock to
the main clock occurs when the edges of the PLL clock and the main clock coincide (after 1 to 8
PLL clocks).
Note:
Before setting the peripheral functions (resources) after the machine clock switching, make
sure that the machine clock has been switched by referring to the MCM bit of the CKSCR.
s Selection of a PLL Clock Multiplier
Set the multiplier selection bits (CS1 and CS0) of the CKSCR to "00B" and "11B" to set one of
the four PLL clock multipliers (1 through 4).