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CHAPTER 2 CPU
2.7.4
Condition Code Register (PS: CCR)
The condition code register (CCR) is an 8-bit register that consists of the following
bits:
Bits that indicate the result of an arithmetic operation and the contents of transfer
data
Bits that control the acceptance of an interrupt request
s Condition Code Register (CCR) Configuration
Refer to the programming manual for details about the status of the condition code register
(CCR) during instruction execution.
Figure 2.7-9 Condition Code Register (CCR) Configuration
r Interrupt enable flag (I)
Interrupts are enabled when the I flag is set to "1", or disabled when the I flag is reset to "0", in
response to any interrupt request other than software interrupts. The I flag is reset to "0" by an
external or software reset.
r Stack flag (S)
This flag indicates the pointer used for a stack operation. The user stack pointer (USP) is valid
if the S flag is reset to "0". The system stack pointer (SSP) is valid if the S flag is set to "1". The
S flag is set to "1" when an interrupt is accepted or when an external or software reset is
asserted.
For more information on the stack pointers, see Sectio
n 2.7.2 "Stack Pointers (USP, SSP)"
r Sticky bit flag (T)
The T flag is set to "1" if the data shifted out of by the carry contains "1" during execution of a
logical or arithmetic right shift instruction. Otherwise, the T flag is reset to "0". The T flag is also
ILM
RP
CCR
PS
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7
bit6
bit5
bit4
bit3
bit2
bit1 bit0
IS
T
N
Z
V
C
Interrupt enable flag
Stack flag
Sticky bit flag
Negative flag
Zero flag
Overflow flag
Carry flag
ILM2 ILM1 ILM0 B4
B3 B2 B1
B0
CCR initial value
X01XXXXX B
X :
Not used
- :
Undefined