23
1.8 Notes on Handling Devices
r Treatment of A/D converter power pin
When the A/D converter is not used, connect the pins as follows: AVcc =Vcc, AVss = AVRH =
AVRL = Vss.
r Notes on external clock
When an external clock is used, the oscillation stabilization wait time is required at power-on
reset or at cancellation of subclock mode or stop mode.
When an external clock is used,
connect only the X0 pin and leave the X1 pin open.
Figure 1.8-1 Sample Application of External Clock
r Power supply pins
When a device has two or more Vcc or Vss pins, the pins that should have equal potential are
connected within the device in order to prevent a latchup or other malfunction.
To reduce
extraneous emission, to prevent a malfunction of the strobe signal due to an increase in the
group level, and to maintain the local output current rating, connect all these power supply pins
to an external power supply and to the same ground.
The current source should be connected to the Vcc and Vss pins of the device with minimum
impedance. It is recommended that a bypass capacitor of about 0.1
F be connected near the
terminals between Vcc and Vss.
r Power-on and power-off sequences
The power to the A/D converter (AVcc, AVR, AVcc) and analog inputs (AN0 to AN7) must be
turned on after the power to the digital circuits (Vcc) is turned on. When turning off the power,
turn off the power to the digital circuits (Vcc) after turning off the power to the A/D converter and
analog inputs. When the power is turned on or off, AVR should not exceed AVcc.
Also, when a pin that is used for analog input is also used as an input port, the input voltage
should not exceed AVcc. (The power to the analog circuits and the power to the digital circuits
can be simultaneously turned on or off.)
r Undefined outputs from Ports 0 and 1
Ports 0 and 1 output undefined signals if the RST pin is "H" during the oscillation stabilization
wait interval of the falling-edge circuit (during power-on rest) after power-on. If the RST pin is
"L", Ports 0 and 1 enter the high-impedance state.
Note that the timing is as shown in
Figure 1.8-2 "Timing Chart for Undefined Outputs from Ports
0 and 1 (if the RST Terminal is "H")" and
Figure 1.8-3 "Timing Chart for High Impedance State
of Ports 0 and 1 (if the RST Terminal is "L")" (applicable models:
MB90F562/B and
MB90V560).
On a model without a falling-edge circuit, Ports 0 and 1 do not output undefined signals because
there is no oscillation stabilization wait interval (applicable models: MB90561/A, MB90562/A,
MB90567/8, and MB90F568).
X0
X1
OPEN
MB90560/565 Series