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型號(hào)：	MB90V560CR
廠(chǎng)商：	FUJITSU LTD
元件分類(lèi)：	微控制器/微處理器
英文描述：	16-BIT, 8 MHz, MICROCONTROLLER, CPGA256
封裝：	PGA-256
文件頁(yè)數(shù)：	343/616頁(yè)
文件大?。?/td>	15240K
代理商：	MB90V560CR

14.5 Operation of the DTP/External Interrupt Circuit

14.5.1 External Interrupt Function

The DTP/external interrupt circuit has an external interrupt function that outputs an

interrupt request when the input signal is input to an external interrupt input pin (INT7

to INT0).

s External Interrupt Function

When the detection condition (level or edge) set in the request level setting register (ELVR) is

input to an external interrupt input pin (INT7 to INT0), the external interrupt request flag bit (ER7

to ER0) corresponding to the pin of the DTP/external interrupt cause register (EIRR) is set to

If the external interrupt request enable bit (EN7 to EN0) corresponding to the external

interrupt input pin (INT7 to INT0) of the DTP/external enable register (ENIR) is set to "1", an

interrupt request is output to the interrupt controller. The interrupt controller determines the

interrupt level (ICR: IL2 to IL0) of interrupt requests from peripheral functions (resources) and

priorities when interrupt requests are output simultaneously. The CPU determines whether to

accept an interrupt request based on the interrupt level mask register (PS: ILM) and interrupt

enable flag (PS: CCR: I). When the CPU accepts an interrupt request, it performs interrupt

processing before branching to the interrupt processing routine.

In the interrupt processing

program, set the corresponding external interrupt request flag bit (ER7 to ER0) to "0" and clear

the interrupt request before returning from the interrupt using an interrupt return instruction.

When the interrupt processing program is activated, be sure to set the external interrupt

request flag bit (EIRR: EN7 to EN0) that caused the activation to "0". It is not possible to

return from an interrupt while the external interrupt request flag bit (EIRR: EN7 to EN0) is set

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