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CHAPTER 13 UART
13.5.1 Reception Interrupt Generation and Flag Set Timing
The following are reception interrupt causes: completion of reception (SSR0/SSR1:
RDRF="1") and occurrence of a reception error (one of SSR0/SSR1: PE, ORE, and FRE
is "1").
s Reception Interrupt Generation and Flag Set Timing
Receive data is stored in the input data register (SIDR0/SIDR1) and the reception data full flag
bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when a stop bit is detected (in
operation mode 0 or 1) or the last bit of data (D7) is detected (in operation mode 2). When a
reception error occurs, one of the reception error flags (PE, ORE, FRE) is set to "1". If any of
the reception error flag bits in each operation mode is set to "1", the value contained in the input
data register (SIDR0/SIDR1) becomes invalid.
r Operation Mode 0 (Asynchronous, Normal Mode)
The reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when a
stop bit is detected. If a reception error is detected, "1" is set to one of the reception error flag
bits (PE, ORE, FRE).
r Operation Mode 1 (Asynchronous, Multiprocessor Mode)
The reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when a
stop bit is detected. If a reception error is detected, "1" is set to either of the reception error flag
bits (ORE, FRE). Parity errors cannot be detected.
r Operation Mode 2 (Synchronous, Normal Mode)
The reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when the
last bit (D7) of receive data is detected.
If a reception error is detected, "1" is set to the
reception error flag bit (ORE). Parity and framing errors cannot be detected.