
463
19.5 Confirming the Automatic Algorithm Execution State
Flash memory contains a hardware sequence for checking the internal flash memory
operating state because the automatic algorithm controls the write/erase flow.
s Hardware Sequence Flag
The hardware sequence flag consists of the four flag bits, DQ7, DQ6, DQ5, and DQ3. These
flag bits have the data polling flag (DQ7) function, toggle bit flag (DQ6) function, time limit
exceeded flag (DQ5) function, and sector erase timer flag (DQ3) function, respectively. These
functions can verify whether the write/chip sector erase is terminated or whether the erase code
write is valid.
The hardware sequence flag can be referenced by accessing/reading the address of the target
sector in the flash memory, after setting the command sequence (see
Table 19.5-1 "Hardware
Sequence Flag Bit Allocation") indicates the hardware sequence flag bit allocation.
Whether the automatic write algorithm or chip/sector erase algorithm is being performed or has
terminated can be determined by checking the hardware sequence flags or the write/erase
status bit (RDY) of the flash memory control register (FMCS). After the write/erase operation is
terminated, the flash memory is returned to the read/reset status. When creating write/erase
programs, perform processing such as data readout after verifying the completion of write/erase
operation by using the hardware sequence flags (DQ7, DQ6, DQ5, and DQ3). Whether the
second sector erase code write or a later one is valid can also be checked by using the
hardware sequence flags.
Table 19.5-1 Hardware Sequence Flag Bit Allocation
Bit No.
7
6
5
4
3
2
1
0
Hardware sequence flag
DQ7
DQ6
DQ5
-
DQ3
-