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型號(hào)：	MB90V560CR
廠商：	FUJITSU LTD
元件分類(lèi)：	微控制器/微處理器
英文描述：	16-BIT, 8 MHz, MICROCONTROLLER, CPGA256
封裝：	PGA-256
文件頁(yè)數(shù)：	298/616頁(yè)
文件大?。?/td>	15240K
代理商：	MB90V560CR

13.6 UART Baud Rates

13.6.1 Baud Rates Determined Using the Dedicated Baud Rate

Generator

This section describes the baud rates that can be set when the clock from the

dedicated baud rate generator is selected as the UART transfer clock.

s Baud Rates Determined Using the Dedicated Baud Rate Generator

When the clock setting bits of the mode register (SMR0/SMR1) are set to "000B-101B", the baud

rate is set by the dedicated baud rate generator.

When the transfer clock is generated by the dedicated baud rate generator, the machine clock is

divided by the machine clock prescaler and then divided by using the transfer clock division ratio

set by the clock selector. The machine clock division ratios are common to the asynchronous

and synchronous baud rates, but the transfer clock division ratio is set by the clock setting bits

(CS2 to CS0) of the mode register (SMR0/SMR1) separately for the asynchronous and

synchronous baud rates.

The actual transfer ratio can be calculated by using the following formulas:

asynchronous baud rate=

φ / (prescaler division ratio)/(asynchronous transfer clock division

synchronous baud rate=

φ / (prescaler division ratio)/(synchronous transfer clock division ratio)

φ : Machine clock frequency

r Division Ratios for the Prescaler (Common to Asynchronous and Synchronous Baud

As listed in Table 13.6-1 "Setting of Each Division Ratio by the Machine Clock Prescaler", the

machine clock division ratio is set by the division ratio setting bits (DIV2 to DIV0) of the

communication prescaler control register (CDCR0/CDCR1).

Table 13.6-1 Setting of Each Division Ratio by the Machine Clock Prescaler

Div: Mchine clock division ratio

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