
145
6.6 Interrupt of Extended Intelligent I/O Service (EI2OS)
6.6.2
Registers of the Extended Intelligent I/O Service (EI2OS)
Descriptor (ISD)
The extended intelligent I/O service (EI2OS) descriptor (ISD) consists of the following
four registers that account for eight bytes in total:
Data counter (DCT: 2 bytes)
I/O register address pointer (I/OA: 2 bytes)
EI2OS status register (ISCS: 1 byte)
Buffer address pointer (BAP: 3 bytes)
The initial values of these registers are undefined.
s Data Counter (DCT)
The DCT is a 16-bit register in which a transfer data byte count can be set. Every time one byte
of data is transferred, the counter is decremented by one. EI2OS terminates when the data
counter reaches "0000H".
Figure 6.6-3 Configuration of DCT
s I/O Register Address Pointer (IOA)
The IOA is a 16-bit register that indicates the lower address (A15 to A0) of the I/O register used
to transfer data to and from the buffer. The upper address (A23 to A16) is 00H. Any I/O from
0000H to FFFFH can be specified by address.
Figure 6.6-4 Configuration of I/O Register Address Pointer (IOA)
s Extended Intelligent I/O Service (EI2OS) Status Register (ISCS)
The ISCS is an 8-bit register. The ISCS indicates the update/fixed for the buffer address pointer
and I/O register address pointer, transfer data format (byte or word), and transfer direction.
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
Initial value
XXXXXXXXXXXXXXXXB
DCT
bit12 bit11
bit9 bit8
bit10
bit15 bit14 bit13
bit4 bit3
bit1 bit0
bit2
bit7 bit6 bit5
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DCTH
DCTL
R/W: Read-write
X : Undefined
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
Initial value
XXXXXXXXXXXXXXXXB
I/OA
bit12 bit11
bit9 bit8
bit10
bit15 bit14 bit13
bit4 bit3
bit1 bit0
bit2
bit7 bit6 bit5
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
I/OAH
I/OAL
R/W: Read-write
X
: Undefined