I/O Section
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
27
$0026
USB Embedded Device Endpoint 0
Data Register 6 (DE0D6)
R: DE0R67
DE0R66
DE0R65
DE0R64
DE0R63
DE0R62
DE0R61
DE0R60
W:
DE0T67
DE0T66
DE0T65
DE0T64
DE0T63
DE0T62
DE0T61
DE0T60
$0027
USB Embedded Device Endpoint 0
Data Register 7 (DE0D7)
R: DE0R77
DE0R76
DE0R75
DE0R74
DE0R73
DE0R72
DE0R71
DE0R70
W:
DE0T77
DE0T76
DE0T75
DE0T74
DE0T73
DE0T72
DE0T71
DE0T70
$0028
USB Embedded Device Endpoint 1/2
Data Register 0 (DE1D0)
R:
W:
DE1T07
DE1T06
DE1T05
DE1T04
DE1T03
DE1T02
DE1T01
DE1T00
$0029
USB Embedded Device Endpoint 1/2
Data Register 1 (DE1D1)
R:
W:
DE1T17
DE1T16
DE1T15
DE1T14
DE1T13
DE1T12
DE1T11
DE1T10
$002A
USB Embedded Device Endpoint 1/2
Data Register 2 (DE1D2)
R:
W:
DE1T27
DE1T26
DE1T25
DE1T24
DE1T23
DE1T22
DE1T21
DE1T20
$002B
USB Embedded Device Endpoint 1/2
Data Register 3 (DE1D3)
R:
W:
DE1T37
DE1T36
DE1T35
DE1T34
DE1T33
DE1T32
DE1T31
DE1T30
$002C
USB Embedded Device Endpoint 1/2
Data Register 4 (DE1D4)
R:
W:
DE1T47
DE1T46
DE1T45
DE1T44
DE1T43
DE1T42
DE1T41
DE1T40
$002D
USB Embedded Device Endpoint 1/2
Data Register 5 (DE1D5)
R:
W:
DE1T57
DE1T56
DE1T55
DE1T54
DE1T53
DE1T52
DE1T51
DE1T50
$002E
USB Embedded Device Endpoint 1/2
Data Register 6 (DE1D6)
R:
W:
DE1T67
DE1T66
DE1T65
DE1T64
DE1T63
DE1T62
DE1T61
DE1T60
$002F
USB Embedded Device Endpoint 1/2
Data Register 7 (DE1D7)
R:
W:
DE1T77
DE1T76
DE1T75
DE1T74
DE1T73
DE1T72
DE1T71
DE1T70
$0030
USB HUB Endpoint 0 Data Register 0
(HE0D0)
R: HE0R07
HE0R06
HE0R05
HE0R04
HE0R03
HE0R02
HE0R01
HE0R00
W:
HE0T07
HE0T06
HE0T05
HE0T04
HE0T03
HE0T02
HE0T01
HE0T00
$0031
USB HUB Endpoint 0 Data Register 1
(HE0D1)
R: HE0R17
HE0R16
HE0R15
HE0R14
HE0R13
HE0R12
HE0R11
HE0R10
W:
HE0T17
HE0T16
HE0T15
HE0T14
HE0T13
HE0T12
HE0T11
HE0T10
$0032
USB HUB Endpoint 0 Data Register 2
(HE0D2)
R: HE0R27
HE0R26
HE0R25
HE0R24
HE0R23
HE0R22
HE0R21
HE0R20
W:
HE0T27
HE0T26
HE0T25
HE0T24
HE0T23
HE0T22
HE0T21
HE0T20
$0033
USB HUB Endpoint 0 Data Register 3
(HE0D3)
R: HE0R37
HE0R36
HE0R35
HE0R34
HE0R33
HE0R32
HE0R31
HE0R30
W:
HE0T37
HE0T36
HE0T35
HE0T34
HE0T33
HE0T32
HE0T31
HE0T30
$0034
USB HUB Endpoint 0 Data Register 4
(HE0D4)
R: HE0R47
HE0R46
HE0R45
HE0R44
HE0R43
HE0R42
HE0R41
HE0R40
W:
HE0T47
HE0T46
HE0T45
HE0T44
HE0T43
HE0T42
HE0T41
HE0T40
$0035
USB HUB Endpoint 0 Data Register 5
(HE0D5)
R: HE0R57
HE0R56
HE0R55
HE0R54
HE0R53
HE0R52
HE0R51
HE0R50
W:
HE0T57
HE0T56
HE0T55
HE0T54
HE0T53
HE0T52
HE0T51
HE0T50
$0036
USB HUB Endpoint 0 Data Register 6
(HE0D6)
R: HE0R67
HE0R66
HE0R65
HE0R64
HE0R63
HE0R62
HE0R61
HE0R60
W:
HE0T67
HE0T66
HE0T65
HE0T64
HE0T63
HE0T62
HE0T61
HE0T60
$0037
USB HUB Endpoint 0 Data Register 7
(HE0D7)
R: HE0R77
HE0R76
HE0R75
HE0R74
HE0R73
HE0R72
HE0R71
HE0R70
W:
HE0T77
HE0T76
HE0T75
HE0T74
HE0T73
HE0T72
HE0T71
HE0T70
$0038
Unimplemented
R:
W:
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)