MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
63
Chapter 8
Clock Generator Module (CGM)
8.1 Introduction
This section describes the clock generator module (CGM). The CGM generates the crystal clock signal,
CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL)
clock, CGMPCLK, divided by two. This is the clock from which the SIM derives the system clocks,
including the bus clock, which is at a frequency of CGMOUT/2. The PLL also generates a CGMVCLK
clock, at 48MHz, for use as the USBCLK. The PLL is a fully functional frequency generator designed for
use with crystals or ceramic resonators.
This CGM is optimized to generate a 48MHz reference frequency for the USB module, from a 6MHz
crystal.
8.2 Features
Features of the CGM include:
VCO Center-Of-Range Frequency tuned to 48MHz for Low-Jitter Clock Reference for USB Module
Low-Frequency Crystal Operation with Low-Power Operation and High-Output Frequency
Resolution
Programmable Reference Divider for Even Greater Resolution
Programmable Prescaler for Power-of-Two Increases in Bus Frequency
Automatic Bandwidth Control Mode for Low-Jitter Operation
Automatic Frequency Lock Detector
CPU Interrupt on Entry or Exit from Locked Condition
8.3 Functional Description
The CGM consists of three major submodules:
Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK and CGMPCLK.
Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the PLL clock, CGMPCLK, divided by two as the base clock, CGMOUT. The SIM derives
the system clocks from CGMOUT.
Figure 8-1
shows the structure of the CGM.