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參數(shù)資料
| 型號(hào)： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 84/178頁(yè) |
| 文件大小： | 925K |
| 代理商： | MC68HC08KH12A |
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Universal Serial Bus Module (USB)
MC68HC08KH12A Data Sheet, Rev. 1.1
84
Freescale Semiconductor
SUSPND — USB Suspend Control Bit
To save power, this read/write bit should be set by the software if at least 3ms constant idle state is
detected on USB bus. Setting this bit puts the transceiver and regulator into a power savings mode.
This bit also determines the latch scheme for the data lines of the root port and the downstream port.
When this bit is 1, the current state shown on the data lines will be reflected to the data register (D+/D–)
directly. When the bit is 0, the data registers are the latched state sampled at the last EOF2 sample
point. The hub repeater’s function is affected by this bit too. The upstream and downstream traffic will
be blocked if this bit is set to 1. When the global resume or the downstream remote wakeup signal is
found by the suspend hub, software is responsible to propagate the traffic between the root port and
the enabled downstream port by setting the RESUMx control bit. Reset clears this bit.
EOF2 is generated by KH12 every millisecond, if SOF is not detected when three or more EOF2 has
occurred, software can set the SUSPND-bit and put KH12 into suspend mode.
D0+/D0– — Root Port Differential Data
These read only bits are the differential data shown on the HUB root ports. When the bit SUSPND is
0, the data is the latched state at the last EOF2 sample point. When the bit SUSPND is 1, the data
reflects the current state on the data line while accessing this register.
9.4.2 USB HUB Downstream Port Control Register (HDP1CR-HDP4CR)
PEN1-PEN4 — Downstream Port Enable Control Bit
This read/write bit determines whether the enabled or disabled state should be assigned to the
downstream port. Setting this bit 1 to enable the port and clear the bit to disable the port. In the enabled
state a full-speed port propagates all downstream signaling, a low-speed port propagates downstream
low-speed packet traffic when preceded by the preamble PID. An enabled port propagates all
upstream signaling including full speed and low speed packets. This bit can be set to 1 by the host
request only. It can be cleared either by hardware when a fault condition was detected or by software
through the host request. Reset clears this bit.
1 = Downstream port is enabled
0 = Downstream port is disabled
Address: $0051
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PEN1
LOWSP1
RST1
RESUM1
SUSP1
0
D1+
D1–
Write:
Reset:
0
0
0
0
0
0
X
X
↓
↓
Address: $0054
Read:
PEN4
LOWSP4
RST4
RESUM4
SUSP4
0
D4+
D4–
Write:
Reset:
0
0
0
0
0
0
X
X
= Unimplemented
X = Indeterminate
Figure 9-5. USB HUB Downstream Port Control Registers
(HDP1CR-HDP4CR)
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| MC68HC08KL8B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
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