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參數(shù)資料
| 型號： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 75/178頁 |
| 文件大小： | 925K |
| 代理商： | MC68HC08KH12A |
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Interrupts
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
75
RDS[3:0] — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects the reference division factor R.
(See
8.3.3 PLL Circuits
and
8.3.6 Programming the PLL
.) RDS[7:0] cannot be written when the PLLON
bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference
divider the same as a value of $01. (See
8.3.7 Special Programming Exceptions
.) Reset initializes the
register to $01 for a default divide value of 1.
NOTE
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
8.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic zero.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMPCLK, divided by two can
be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software
performance or from exceeding stack limitations.
NOTE
Software can select the CGMPCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
8.7 Special Modes
The WAIT instruction puts the MCU in low-power-consumption standby modes.
8.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would also be the case when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK, or LOCK is lost.
8.7.2 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
7.7.3 Break Flag Control Register (BFCR)
.)
To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
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