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參數(shù)資料
| 型號(hào)： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 50/178頁(yè) |
| 文件大小： | 925K |
| 代理商： | MC68HC08KH12A |
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System Integration Module (SIM)
MC68HC08KH12A Data Sheet, Rev. 1.1
50
Freescale Semiconductor
Figure 7-7. POR Recovery
The COP module is disabled if the RST pin or the IRQ1/V
PP
pin is held at V
DD
+ V
HI
while the MCU is in
monitor mode. The COP module can be disabled only through combinational logic conditioned with the
high voltage signal on the RST or the IRQ1/V
PP
pin. This prevents the COP from becoming disabled as
a result of external noise. During a break state, V
DD
+ V
HI
on the RST pin disables the COP module.
7.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the reset status register (RSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction
as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
7.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down
the RST pin for all internal reset sources.
7.3.2.5 Universal Serial Bus Reset
The USB module will detect a reset signal on the bus by the presence of an extended SE0 at the USB
data pins of the upstream port. The reset signaling is specified to be present for a minimum of 10 ms. An
active device (powered and not in the suspend state) seeing a single-ended zero on its USB data inputs
for more than 2.5
μ
s may treat that signal as a reset, but must have interpreted the signaling as a reset
within 5.5
μ
s. For USB device, an SE0 condition between 4 and 8 low speed bit times or 32 and 64 high
speed bit times represents a valid USB reset. After the reset is removed, the device will be in the attached,
but not yet addressed or configured state (refer to Section 9.1 of the USB specification). The device must
be able to accept device address via a SET_ADDRESS command (refer to section 9.4 of the USB
specification) no later than 10 ms after the reset is removed.
PORRST
OSC1
CGMXCLK
CGMOUT
RST
IAB
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE
$FFFF
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC08KL8B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
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