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參數(shù)資料
| 型號(hào)： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 98/178頁(yè) |
| 文件大?。?/td> | 925K |
| 代理商： | MC68HC08KH12A |
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Universal Serial Bus Module (USB)
MC68HC08KH12A Data Sheet, Rev. 1.1
98
Freescale Semiconductor
9.5.5 USB Embedded Device Control Register 1 (DCR1)
T1SEQ — Embedded Device Endpoint 1/2 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next
IN transaction directed to embedded device Endpoint 1 or 2. Toggling of this bit must be controlled by
software. Reset clears this bit.
1 = DATA1 Token active for next embedded device Endpoint 1/2 transmit
0 = DATA0 Token active for next embedded device Endpoint 1/2 transmit
ENDADD — Endpoint Address Select
This read/write bit specifies whether the data inside the registers DE1D0-DE1D7 are used for
embedded device Endpoint 1 or 2. If all the conditions for a successful Endpoint 2 USB response to a
host’s IN token are satisfied (TXD1F=0, TX1E=1, DSTALL2=0, and ENABLE2=1) except that the
ENDADD bit is configured for Endpoint 1, the USB responds with a NAK handshake packet. Reset
clears this bit.
1 = The data buffers are used for embedded device Endpoint 2
0 = The data buffers are used for embedded device Endpoint 1
TX1E — Embedded Device Endpoint 1/2 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host controller sends an IN token to
Endpoint 1 or Endpoint 2 of the embedded device. The appropriate endpoint enable bit, ENABLE1 or
ENABLE2 bit in the DCR2 register, should also be set. Software should set the TX1E bit when data is
ready to be transmitted. It must be cleared by software when no more data needs to be transmitted.
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake to any Endpoint 1 or
Endpoint 2 directed IN tokens. Reset clears this bit.
1 = Data is ready to be sent.
0 = Data is not ready. Respond with NAK.
TP1SIZ3-TP1SIZ0 — Embedded Device Endpoint 1/2 Transmit Data
Packet Size
These read/write bits store the number of transmit data bytes for the next IN token request for
embedded device Endpoint 1 or Endpoint 2. These bits are cleared by reset.
Address: $004C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
T1SEQ
ENDADD
TX1E
0
TP1SIZ3
TP1SIZ2
TP1SIZ1
TP1SIZ0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-20. USB Embedded Device Control Register 1 (DCR1)
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| MC68HC08KL8B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
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| MC68HC08LJ12CFB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Addendum to MC68HC908LJ12 Technical Data |
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