
Functional Description
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
65
8.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
8.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
8.3.3 PLL Circuits
The PLL consists of these circuits:
Voltage-controlled oscillator (VCO)
Reference divider
Frequency prescaler
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a
range from roughly 40MHz to 56MHz, f
VRS
. Modulating the voltage on the CGM/XFC pin changes the
frequency within this range. By design, f
VRS
is tuned to a nominal center-of-range frequency of 48MHz.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
f
RCLK
, and is fed to the PLL through a programmable modulo reference divider, which divides f
RCLK
by a
factor R. This feature allows frequency steps of higher resolution. The divider’s output is the final
reference clock, CGMRDV, running at a frequency f
RDV
= f
RCLK
/R.
The VCO’s output clock, CLK, running at a frequency f
VCLK
is fed back through a programmable prescale
divider and a programmable modulo divider. The prescaler divides the VCO clock by a power-of-two
factor P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output is the VCO
feedback clock, CGMVDV, running at a frequency f
VDV
= f
VCLK
/(N
×
2
P
). (See
8.3.6 Programming the PLL
for more information.)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGM/XFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on