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參數(shù)資料
| 型號： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 96/178頁 |
| 文件大?。?/td> | 925K |
| 代理商： | MC68HC08KH12A |
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Universal Serial Bus Module (USB)
MC68HC08KH12A Data Sheet, Rev. 1.1
96
Freescale Semiconductor
TXD0IE — Embedded Device Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the Transmit Embedded Device Endpoint 0 to generate CPU interrupt
requests when the TXD0F bit becomes set. Reset clears the TXD0IE bit.
1 = Transmit Embedded Device Endpoint 0 can generate a CPU interrupt request
0 = Transmit Embedded Device Endpoint 0 cannot generate a CPU interrupt request
RXD0IE — Embedded Device Endpoint 0 Receive Interrupt Enable
This read/write bit enables the Receive Embedded Device Endpoint 0 to generate CPU interrupt
requests when the RXD0F bit becomes set. Reset clears the RXD0IE bit.
1 = Receive Embedded Device Endpoint 0 can generate a CPU interrupt request
0 = Receive Embedded Device Endpoint 0 cannot generate a CPU interrupt request
TXD0FR — Embedded Device Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set. Writing a logic 0 to TXD0FR has
no effect. Reset clears this bit.
RXD0FR — Embedded Device Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set. Writing a logic 0 to RXD0FR
has no effect. Reset clears this bit.
9.5.3 USB Embedded Device Interrupt Register 1 (DIR1)
TXD1F — Embedded Device Endpoint 1/2 Data Transmit Flag
This read only bit is shared by Endpoint 1 and Endpoint 2 of the embedded device. It is set after the
data stored in the shared Endpoint 1/2 transmit buffer of the embedded device has been sent and an
ACK handshake packet from the host is received. Once the next set of data is ready in the transmit
buffers, software must clear this flag by writing a logic 1 to the TXD1FR bit. To enable the next data
packet transmission, TX1E must also be set. If TXD1F bit is not cleared, a NAK handshake will be
returned in the next IN transaction. Reset clears this bit. Writing to TXD1F has no effect.
1 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device has occurred
0 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device has not occurred
TXD1IE — Embedded Device Endpoint 1/2 Transmit Interrupt Enable
This read/write bit enables the USB to generate CPU interrupt requests when the shared Transmit
Endpoint 1/2 interrupt flag bit of the embedded device (TXD1F) becomes set. Reset clears the TXD1IE
bit.
1 = Transmit embedded device Endpoints 1 and 2 can generate a CPU interrupt request
0 = Transmit embedded device Endpoints 1 and 2 cannot generate a CPU interrupt request
TXD1FR — Embedded Device Endpoint 1/2 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD1F bit if it is set. Writing a logic 0 to TXD1FR has
no effect. Reset clears this bit.
Address: $004A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TXD1F
0
0
0
TXD1IE
0
0
0
Write:
TXD1FR
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-18. USB Embedded Device Interrupt Register 1 (DIR1)
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