參數(shù)資料
型號(hào)： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 104/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
104 of 110
continued >>
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
22. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. Supported microprocessor and EPP interface
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 5. Connection scheme for detecting the parallel
interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 6. EEPROM memory organization diagram . . . . .10
Table 7. Product information field byte allocation . . . . .11
Table 8. Product information field byte description . . . .11
Table 9. Product type identification definition . . . . . . . .11
Table 10. Byte assignment for register initialization at
start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 11. Shipment content of StartUp
configuration file . . . . . . . . . . . . . . . . . . . . . . .12
Table 12. Byte assignment for register initialization at
startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 13. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .15
Table 14. Associated FIFO buffer registers and flags . . .16
Table 15. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .17
Table 16. Interrupt control registers . . . . . . . . . . . . . . . .17
Table 17. Associated Interrupt request system registers
and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 18. Associated timer unit registers and flags . . . . .23
Table 19. Signal on pins during Hard power-down . . . . .23
Table 20. Pin TX1 configurations . . . . . . . . . . . . . . . . . .27
Table 21. Pin TX2 configurations . . . . . . . . . . . . . . . . . .27
Table 22. TX1 and TX2 source resistance of n-channel
driver transistor against
GsCfgCW or GsCfgMod . . . . . . . . . . . . . . . . .28
Table 23. Gain factors for the internal amplifier . . . . . . . .32
Table 24. DecoderSource[1:0] values . . . . . . . . . . . . . . .34
Table 25. ModulatorSource[1:0] values . . . . . . . . . . . . . .34
Table 26. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .34
Table 27. Register settings to enable use of the analog
circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 28. Dedicated address bus: assembling the
register address . . . . . . . . . . . . . . . . . . . . . . . .37
Table 29. Multiplexed address bus: assembling the
register address . . . . . . . . . . . . . . . . . . . . . . . .37
Table 30. Behavior and designation of register bits . . . . .38
Table 31. MFRC500 register overview . . . . . . . . . . . . . .39
Table 32. MFRC500 register flags overview . . . . . . . . . .41
Table 33. Page register (address: 00h, 08h, 10h, 18h,
20h, 28h, 30h, 38h) reset value: 1000 0000b,
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .43
Table 34. Page register bit descriptions . . . . . . . . . . . . .43
Table 35. Command register (address: 01h)
reset value: x000 0000b, x0h bit allocation . . . 44
Table 36. Command register bit descriptions . . . . . . . . . 44
Table 37. FIFOData register (address: 02h)
reset value: xxxx xxxxb, xxh bit allocation . . . 44
Table 38. FIFOData register bit descriptions . . . . . . . . . 44
Table 39. PrimaryStatus register (address: 03h)
reset value: 0000 0101b, 05h bit allocation . . 45
Table 40. PrimaryStatus register bit descriptions . . . . . . 45
Table 41. FIFOLength register (address: 04h)
reset value: 0000 0000b, 00h bit allocation . . 46
Table 42. FIFOLength bit descriptions . . . . . . . . . . . . . . 46
Table 43. SecondaryStatus register (address: 05h)
reset value: 01100 000b, 60h bit allocation . . . 46
Table 44. SecondaryStatus register bit descriptions . . . . 46
Table 45. InterruptEn register (address: 06h)
reset value: 0000 0000b, 00h bit allocation . . 47
Table 46. InterruptEn register bit descriptions . . . . . . . . 47
Table 47. InterruptRq register (address: 07h)
reset value: 0000 0000b, 00h bit allocation . . 47
Table 48. InterruptRq register bit descriptions . . . . . . . . 47
Table 49. Control register (address: 09h)
reset value: 0000 0000b, 00h bit allocation . . 48
Table 50. Control register bit descriptions . . . . . . . . . . . 48
Table 51. ErrorFlag register (address: 0Ah)
reset value: 0100 0000b, 40h bit allocation . . 49
Table 52. ErrorFlag register bit descriptions . . . . . . . . . . 49
Table 53. CollPos register (address: 0Bh)
reset value: 0000 0000b, 00h bit allocation . . 50
Table 54. CollPos register bit descriptions . . . . . . . . . . . 50
Table 55. TimerValue register (address: 0Ch)
reset value: xxxx xxxxb, xxh bit allocation . . . 50
Table 56. TimerValue register bit descriptions . . . . . . . . 50
Table 57. CRCResultLSB register (address: 0Dh)
reset value: xxxx xxxxb, xxh bit allocation . . . 50
Table 58. CRCResultLSB register bit descriptions . . . . . 50
Table 59. CRCResultMSB register (address: 0Eh)
reset value: xxxx xxxxb, xxh bit allocation . . . 51
Table 60. CRCResultMSB register bit descriptions . . . . 51
Table 61. BitFraming register (address: 0Fh)
reset value: 0000 0000b, 00h bit allocation . . 51
Table 62. BitFraming register bit descriptions . . . . . . . . . 51
Table 63. TxControl register (address: 11h)
reset value: 0101 1000b, 58h bit allocation . . 52
Table 64. TxControl register bit descriptions . . . . . . . . . 52
Table 65. CwConductance register (address: 12h)
reset value: 0011 1111b, 3Fh bit allocation . . . 53
Table 66. CwConductance register bit descriptions . . . . 53
Table 67. PreSet13 register (address: 13h)
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