參數(shù)資料
型號： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 12/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
12 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
The byte assignment is shown in
Table 10
.
Table 10.
EEPROM byte address
10h (block 1, byte 0)
11h
…
2Fh (block 2, byte 15)
9.2.2.2
Factory default StartUp register initialization file
During the production tests, the StartUp register initialization file is initialized using the
default values shown in
Table 11
. During each power-up and initialization phase, these
values are written to the MFRC500’s registers.
Byte assignment for register initialization at start-up
Register address
10h
11h
…
2Fh
Remark
skipped
copied
…
copied
Table 11.
EEPROM
byte
address
10h
11h
Shipment content of StartUp configuration file
Register
address
Value
Symbol
Description
10h
11h
00h
58h
Page
TxControl
free for user
transmitter pins TX1 and TX2 are switched off, bridge driver
configuration, modulator driven from internal digital circuitry
source resistance of TX1 and TX2 is set to minimum
-
12h
13h
12h
13h
3Fh
3Fh
CwConductance
PreSet13
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
19h
13h
00h
00h
00h
73h
08h
ADh
FFh
00h
41h
PreSet14
ModWidth
PreSet16
PreSet17
Page
RxControl1
DecoderControl
BitPhase
RxThreshold
PreSet1D
RxControl2
-
pulse width for Miller pulse encoding is set to standard configuration
-
-
free for user
ISO/IEC 14443 A is set and internal amplifier gain is maximum
bit-collisions always evaluate to HIGH in the data bit stream
BitPhase[7:0] is set to standard configuration
MinLevel[3:0] and CollLevel[3:0] are set to maximum
-
use Q-clock for the receiver, automatic receiver off is switched on,
decoder is driven from internal analog circuitry
automatic Q-clock calibration is switched on
free for user
frame guard time is set to six bit-clocks
channel redundancy is set using ISO/IEC 14443 A
CRC preset value is set using ISO/IEC 14443 A
CRC preset value is set using ISO/IEC 14443 A
-
pin MFOUT is set LOW
-
free for user
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
00h
00h
06h
03h
63h
63h
00h
00h
00h
00h
ClockQControl
Page
RxWait
ChannelRedundancy
CRCPresetLSB
CRCPresetMSB
PreSet25
MFOUTSelect
PreSet27
Page
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