參數(shù)資料
型號： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 56/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
56 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
10.5.4.4
BitPhase register
Selects the bit-phase between transmitter and receiver clock.
Table 81.
Bit
Symbol
Access
Table 82.
Bit
7 to 0
10.5.4.5
RxThreshold register
Selects thresholds for the bit decoder.
Table 83.
Bit
Symbol
Access
Table 84.
Bit
7 to 4
10.5.4.6
PreSet1D Register
These bit settings must not be changed.
Table 85.
Bit
Symbol
Access
Table 86.
Bit
7 to 0
BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation
7
6
5
4
BitPhase[7:0]
3
2
1
0
R/W
BitPhase register bit descriptions
Symbol
Description
BitPhase[7:0]
defines the phase relationship between transmitter and receiver clock
Remark:
The correct value of this register is essential for proper
operation.
RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation
7
6
5
4
MinLevel[3:0]
R/W
3
2
1
0
CollLevel[3:0]
R/W
RxThreshold register bit descriptions
Symbol
Description
MinLevel[3:0]
the minimum signal strength the decoder will accept. If the signal
strength is below this level, it is not evaluated.
CollLevel[3:0]
the minimum signal strength the decoder input that must be reached
by the weaker half-bit of the Manchester encoded signal to generate
a bit-collision (relative to the amplitude of the stronger half-bit)
3 to 0
PreSet1D register (address: 1Dh) reset value: 0000 0000b, 00h bit allocation
7
6
5
00000000
4
3
2
1
0
R/W
PreSet1D register bit descriptions
Symbol
Value
00000000
0
Description
these values must not be changed
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