參數(shù)資料
型號(hào)： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁(yè)數(shù)： 57/110頁(yè)
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
57 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
10.5.4.7
RxControl2 register
Controls decoder behavior and defines the input source for the receiver.
Table 87.
Bit
Symbol
Access
Table 88.
Bit
7
[1]
I-clock and Q-clock are 90
°
phase-shifted from each other.
10.5.4.8
ClockQControl register
Controls clock generation for the 90
°
phase-shifted Q-clock.
Table 89.
Bit
Symbol
Access
Table 90.
Bit
7
RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation
7
6
5
4
RcvClkSelI
RxAutoPD
R/W
R/W
3
2
1
0
0000
R/W
DecoderSource[1:0]
R/W
RxControl2 register bit descriptions
Symbol
RcvClkSelI
Value
1
0
1
Description
I-clock is used as the receiver clock
[1]
Q-clock is used as the receiver clock
[1]
receiver circuit is automatically switched on before
receiving and switched off afterwards. This can be used to
reduce current consumption.
receiver is always activated
these values must not be changed
selects the source for the decoder input
LOW
internal demodulator
a subcarrier modulated Manchester encoded signal on
pin MFIN
a baseband Manchester encoded signal on pin MFIN
6
RxAutoPD
0
-
5 to 2
1 to 0
0000
DecoderSource[1:0]
00
01
10
11
ClockQControl register (address: 1Fh) reset value: 000x xxxxb, xxh bit allocation
7
6
5
4
ClkQ180Deg
ClkQCalib
0
R
R/W
R/W
3
2
1
0
ClkQDelay[4:0]
D
ClockQControl register bit descriptions
Symbol
Value
ClkQ180Deg
1
Description
Q-clock is phase-shifted more than 180
°
compared to the
I-clock
Q-clock is phase-shifted less than 180
°
compared to the
I-clock
Q-clock is automatically calibrated after the reset phase and
after data reception from the card
no calibration is performed automatically
this value must not be changed
this register shows the number of delay elements used to
generate a 90
°
phase-shift of the I-clock to obtain the
Q-clock. It can be written directly by the microprocessor or
by the automatic calibration cycle.
0
6
ClkQCalib
0
1
-
-
5
4 to 0
0
ClkQDelay[4:0]
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